Internal Architecture - Fujitsu FR60 Hardware Manual

3.2

Internal Architecture

The FR family CPU is a high-performance core based on RISC architecture and
advanced instructions for embedded applications.
■ Features
❍ RISC architecture used
Basic instruction: One instruction per cycle
❍ 32-bit architecture
General-purpose register: 32 bits x 16
❍ 4 G bytes linear memory space
❍ Multiplier installed
• 32-bit by 32-bit multiplication: 5 cycles
• 16-bit by 16-bit multiplication: 3 cycles
❍ Enhanced interrupt processing function
• Quick response speed: 6 cycles
• Support of multiple interrupts
• Level mask function: 16 levels
❍ Enhanced instructions for I/O operations
• Memory-to-memory transfer instruction
• Bit-processing instructions
❍ Efficient code
Basic instruction word length: 16 bits
❍ Low-power consumption
Sleep and stop modes
❍ Gear function
CHAPTER 3 CPU AND CONTROL UNITS
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