Figure 4.2A Reset Cause Bit Block Diagram; Figure 4.2B Wdtc (Watch-Dog Timer Control Register); Table 4.2B Reset Cause Bits - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Power on
Hardware standby
Power-on
release detection
detection circuit
S R
F / F
Q
2
F MC-16LX internal bus
Address: 0000A8
H
Read/write
Initial value
When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer control
register are set. Therefore, if an external reset request and a watch-dog reset occur at the same time, both
the ERST and WRST bits are set to 1.
A power-on reset is an exception; while the PONR bit is 1, the values of other bits do not indicate the
correct reset causes. Therefore, design software so that the other reset cause bit values are ignored while
the PONR bit is set to 1.
Reset cause
Power-on
Hardware standby
Watch-dog timer
External pin
RST bit
(An asterisk (*) in the table means that the previous value is maintained.)
Note: A reset cause bit is cleared only by reading the watch-dog timer control register. Thus,
once a reset occurs, the corresponding reset cause bit remains 1 even if another reset
cause occurs.
MB90580 Series
HSTX pin
RSTX pin
HSTX=LÆH RSTX=L
External reset
request detection
circuit
S R
S R
F / F
F / F
Q
Q

Figure 4.2a Reset cause bit block diagram

7 6
PONR STBR WRST
(R) (R)
(X) (X)

Figure 4.2b WDTC (watch-dog timer control register)

Table 4.2b Reset cause bits

PONR
1
*
*
*
*
Without periodic clear
Watch-dog timer
reset detection circuit
circuit
S R S
F / F F / F
Q Q
5 4 3
ERST SRST
(R) (R) (R)
(X) (X) (X)
STBR WRST
1 *
* 1
* *
* *
4.2 Reset Causes
RST bit set
STBYC.RST bit
write detection circuit
R WTC register
Delay
circuit
WTC register read
2 1 0
WTE WT1 WT0
(W) (W) (W)
(1) (1) (1)
ERST SRST
* *
* *
1 *
* 1
Chapter 4: Clock and Reset
Bit No.
WDTC
49