Table of Contents
Advertisement
5.1.2 CIF1 (CCNT) Register / Clock Control Register
The CLOCK CONTROL Register is writeable in DEFAULT_CONFIG (CCSV[5:0] = 00 0000)
or CONFIG state (CCSV[5:0] = 00 1111), only
Address
31
0x0004
R:
Read only
R/W:
Read/Write
MCU-AN-300015-E-V11
MB91F465XA EMULATION
Chapter 5 Appendix
9
8
7
RSV
SDIV[1:0]
R/W
R/W
6
5
4
3
RSV
STOP
RCLK
PMUL[1:0]
R/W
R/W
R/W
R/W
bit0
PON
PLL Oscillator Enable
0
Stop PLL oscillator
1
Enable PLL oscillator
bit1
SSEL
System Clock Selection
0
Select the oscillation clock (X0/X1)
1
Select the PLL clock
bit3 - bit2
PMUL[1:0]
PLL Multiplier Selection
0
0
X0/X1 (4MHz) x 20 (80MHz)
0
1
X0/X1 (5MHz) x 16 (80MHz)
1
0
X0/X1 (8MHz) x 10 (80MHz)
1
1
X0/X1 (10MHz) x 8 (80MHz)
bit4
RCLK
RAM Clock Selection (MB88121A/B only)
0
Select System Clock
1
Select System Clock divided by 2
bit5
STOP
Clock Stop
0
Supply the system clock for FlexRay Controller
1
Stop the system clock for FlexRay Controller
bit6
RSV
Reserved
These bits are reserved. Always write "0". "0" is read.
bit8 - bit7
SDIV[1:0]
Division for system clock (MB88121A/B only)
0
0
System clock is divided by 1
0
1
System clock is divided by 2
1
0
System clock is divided by 4
1
1
System clock is divided by 8
bit31 - bit9
RSV
Reserved
These bits are reserved. Always write "0". "0" is read.
- 28 -
© Fujitsu Microelectronics Europe GmbH
Initial value
2
1
0
SSEL
PON
0x00000000
R/W
R/W
Advertisement
Table of Contents
