Fig. 3.8 Configuration Of Reset Factor Bit (Watchdog Timer Control Register); Table 3-4 Correspondence Of Reset Factor Bit Value And Reset Factor - Fujitsu MB90420/5 (A) Series Hardware Manual

n Correspondence of reset factor bit and reset factor
Figure 3.8 shows the configuration of the reset factor bit of the watchdog timer control register (WDTC), and
the Table 3-4 shows the correspondence of the reset bit value and the reset factor. For detail, see Section
7.1.
Watchdog timer control register (WDTC)
Address bit 15
0000A8
H
R : Read only
W : Write only
X : Undefined

Fig. 3.8 Configuration of Reset Factor Bit (Watchdog Timer Control Register)

Table 3-4 Correspondence of Reset Factor Bit Value and Reset Factor

Power-on reset request
Low voltage detection reset request
Reset request by watchdog timer overflow
External reset request from RSTX pin
CPU Operation detection reset request
Software reset request
* : The previous state is held
X : Undefined
*1 : At a low voltage detection reset request, the LVRF bit of the low voltage/CPU operation detection
reset control register (LVRC) is also set to 1.
*2 : At a CPU operation detection reset request, the CPUF bit of the low voltage/CPU operation
detection reset control register (LVRC) is also set to 1.
n Notes on reset factor bit
• At plural reset factor
When plural reset factors occur, the corresponding reset factor bits of the watchdog timer control register
(WDTC) are set to "1". For example, when an external reset request from the RSTX pin and a watchdog
timer overflow occur simultaneously, the ERST and WRST bits are set to "1".
• Power-on reset
At power-on reset, the PONR bit is set to "1", and reset factor bits other than the PONR bit are undefined.
Consequently, the software must ignore reset factor bits other than the PONR bit when the PONR bit is "1".
• Clearing reset factor bit
The reset factor bits are cleared only when the watchdog timer control register (WDTC) is read. Even
when another reset is caused by an other factor afterward, the flag set at the bit corresponding to each
reset factor is not cleared (flag remains 1).
Note: When the power is turned on, under condition that no power-on reset occurs, the value of the WDTC
register is not assured.
bit 8 bit 7 bit 6
(TBTC) PONR —
R —
Reset Factor
*1
*2
RESET
bit 5 bit 4 bit 3 bit 2
WRST ERST SRST WTE
R R R W
PONR
1
*
*
*
3-11
Initial value
bit 1 bit 0
WT1 WT0 X-XXX111
W W
WRST ERST SRST
X X X
1 * *
* 1 *
* * 1
B