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CHAPTER 6 LOW POWER CONSUMPTION MODE
6.3
Low Power Consumption Mode Control Register (LPMCR)
The low power consumption mode control register (LPMCR) switches to or releases low
power consumption mode. It is also used to set the number of CPU clock pulses the
CPU is to be halted during CPU intermittent mode.
■ Low Power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of the Low Power Consumption Mode Control Register (LPMCR)
bit
15
Address
(CKSCR)
0000A0
H
R/W:
W:
: Initial value
94
7
6
5
STP
SLP
SPL
W
W
R/W
Read/write
Write-only
4
3
2
1
RST TMDX CG1
CG0
RESV
W
W
R/W
R/W
RESV
Reserved bit
1 must always be written to these bits.
CPU halt clock pulses selection bits
CG1
CG0
0
0
0 clock pulse (CPU clock = Peripheral clock)
0
1
9 clock pulses (CPU clock: Peripheral clock = 1: 3 to 4 approx.)
1
0
17 clock pulses (CPU clock: Peripheral clock = 1: 5 to 6 approx.)
33 clock pulses (CPU clock: Peripheral clock = 1: 9 to 10 approx.)
1
1
TMDX
Time-base timer bit
0
Switch to time-base timer mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of 3 machine cycles.
1
No change, no effect on operation
SPL
Pin state setting bit (for time-base timer mode and stop mode)
0
Retained
1
High-impedance
SLP
Sleep bit
0
No change, no effect on operation
1
Switch to sleep mode
STP
0
No change, no effect on operation
1
Switch to stop mode
0
Initial value
00011000
B
R/W
Stop bit
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