Figure 3.7.3 Standby Control Register (Stbc) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.7 Standby Modes (Low-power Consumption)
3.7.3 Standby Control Register (STBC)
The standby control register (STBC) controls the changing to sleep mode or stop
mode, sets the pin states in stop mode, and initiates software resets.
n Standby Control Register (STBC)
Address
R/W : Readable and writable
W
—
X
70
CHAPTER 3 CPU
Bit 7 Bit 6
0008 STP SLP
H
W W
: Write-only
: Unused
: Indeterminate
: Initial value

Figure 3.7.3 Standby Control Register (STBC)

Bit 5 Bit 4 Bit 3 Bit 2
SPL RST — —
R/W W
RST
Read
0 —
1 Reading always returns "1".
SPL
0 External pins hold their states prior to entering stop mode.
1 External pins go to high-impedance state on entering stop mode.
SLP
Read
0 Reading always returns "0".
1 —
STP
Read
0 Reading always returns "0".
1 —
Bit 1 Bit 0 Initial value
— — 0001XXXX
Software reset bit
Write
Generates a reset signal for
four instruction cycles.
No effect on operation
Pin state specification bit
Sleep bit
Write
No effect on operation
Change to sleep mode.
Stop bit
Write
No effect on operation
Change to stop mode.
B
MB89620 series