I 2 C Bus Clock Control Register 0 To 2 (Iccr0 To Iccr2) - Fujitsu F2MC-16LX Hardware Manual

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CHAPTER 22 I C INTERFACE
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22.2.3 I C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2)
The configuration and functions of I
ICCR2) are described.
2
I C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2)
Figure 22.2-7 shows the bit configuration of I
Figure 22.2-7 Bit Configuration of I
ch0:000072
ch1:000078
ch2:00007E
The functions of I
[bit 7, bit 6] undefinition bit
The read value is irregular. Nothing is affected when it is written.
[bit 5] EN: ENable
It is an operation permission bit in the I
0
1
• When "0", each bit of IBSR register and IBCR register (except BER and BEIE bits) is cleared.
• Is cleared when BER bit is set.
[bit 4 to bit 0] CS4 to CS0:Clock Period Select 4-0
It is the bit which sets the serial clock frequency. The frequency fsck in the shift clock is set as shown in
the next formula.
Note:
The cycle + 4 is minimum overhead for checking that the output level of SCL pin has changed. If
delay is longer on the rising edge of SCL pin, or a slave device delays a clock, it exceeds this value.
Note that the frequency of the serial clock must be set to 100 kHz or less.
m and n for CS4 to CS0 is as shown in Table 22.2-1.
532
2
C bus clock control register 0 to 2 (ICCR0 to
2
C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2)
7 6 5 4
H
EN CS4 CS3 CS2 CS1 CS0
H
H
R/W R/W R/W R/W R/W R/W
2
C bus clock control registers 0 to 2 (ICCR0 to ICCR2) are described below.
Operation disabled
Operation enabled
fsck
2
C bus clock control registers 0 to 2 (ICCR0 to ICCR2).
3 2 1 0
ICCR0 to ICCR2
I
Initial value
2
C interface.
φ
φ
: Machine clock
m n
4
2
C Clock control register
XX0XXXXX
B