Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - ST STM32F100 Series Reference Manual

Reset and clock control (RCC)
Bit 5 IOPDRST: IO port D reset
Bit 4 IOPCRST: IO port C reset
Bit 3 IOPBRST: IO port B reset
Bit 2 IOPARST: I/O port A reset
Bit 1
Bit 0 AFIORST: Alternate function I/O reset
6.3.5

APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
CECR DAC PWR
ST
RST RST
Res.
rw rw rw
15 14 13 12
SPI3 SPI2
RST RST
Reserved
rw rw
Bit 31
Bit 30 CECRST: CEC reset
Bit 29 DACRST: DAC interface reset
88/709
Set and cleared by software.
0: No effect
1: Reset I/O port D
Set and cleared by software.
0: No effect
1: Reset I/O port C
Set and cleared by software.
0: No effect
1: Reset I/O port B
Set and cleared by software.
0: No effect
1: Reset I/O port A
Reserved, always read as 0.
Set and cleared by software.
0: No effect
1: Reset Alternate Function
27 26 25
BKP
RST
Reserved
rw
11 10 9
WWDG
RST
Reserved
rw
Reserved, always read as 0.
Set and cleared by software.
0: No effect
1: Reset CEC
Set and cleared by software.
0: No effect
1: Reset DAC interface
24 23 22 21
I2C2 I2C1
RST RST
rw rw
8 7 6 5
TIM14 TIM13 TIM12 TIM7
RST RST RST RST
rw rw rw rw
RM0041 Rev 6
20 19 18
UART5 UART4 USART3
RST RST RST
rw rw rw
4 3 2
TIM6 TIM5 TIM4
RST RST RST
rw rw rw
RM0041
17 16
USART2
RST
Res.
rw
1 0
TIM3 TIM2
RST RST
rw rw