Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - ST STM32L0x3 Reference Manual

RM0367
Bit 14 USART1RST: USART1 reset
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI 1 reset
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC interface reset
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM22RST: TIM22 timer reset
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21RST: TIM21 timer reset
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: System configuration controller reset
7.3.11

APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
PWR
LPTIM1 I2C3R DACR
RST ST ST
RST
rw rw rw rw
15 14 13 12
SPI2R
Res. Res. Res.
ST
rw
This bit is set and cleared by software.
0: No effect
1: Reset USART1
This bit is set and cleared by software.
0: No effect
1: Reset SPI 1
This bit is set and cleared by software.
0: No effect
1: Reset ADC interface
This bit is set and cleared by software.
0: No effect
1: Reset TIM22 timer
This bit is set and cleared by software.
0: No effect
1: Reset TIM21 timer
This bit is set and cleared by software.
0: No effect
1: Reset System configuration controller
27 26 25
CRSR
Res. Res.
ST
rw
11 10 9
WWDG
Res. LCDRST
RST
rw rw
24 23 22 21
I2C2R I2C1R
Res. USBRST
ST ST
rw rw rw
8 7 6 5
TIM7R
Res. Res. Res. ST
rw
RM0367 Rev 7
Reset and clock control (RCC)
20 19 18
USART5 USART4 LPUART1
RST RST RST
rw rw rw
4 3 2
TIM6RS
T Res. Res.
rw
17 16
USART2
Res.
RST
rw
1 0
TIM3RS
TIM2
T
RST
rw rw
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