Debug Management; Introduction; Swj Debug Port (Serial Wire And Jtag); Tpiu Trace Port - ST STM32H7 3 Series Application Note

Debug management

5 Debug management
5.1

Introduction

The host/target interface is the hardware equipment that connects the host to the application
board. This interface is made of three components: a hardware debug tool, a JTAG or SW
connector and a cable connecting the host to the debug tool.
connection of the host to the evaluation board.
5.2

SWJ debug port (serial wire and JTAG)

The core of STM32H743/753xx devices integrates the Serial Wire / JTAG Debug Port (SWJ-
DP). It is an ARM
and a 2-pin SW-DP interface.
• The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
•
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
For more details on the SWJ debug port refer to RM0433 SWJ debug port section (serial
wire and JTAG).
5.2.1

TPIU trace port

The TPIU trace port comprises four data outputs plus one clock output. The number of data
outputs can be configured by software and unused signals can be reused as GPIOs. If the
trace port is not required, all the signals can be used as GPIOs. By default, the trace port is
disabled.
The trace data and clock can operate at up to 133 MHz. As a result, care must be taken with
the layout of these signals: the trace connector should be located as close as possible to the
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Figure 16. Host to board connection

®
standard CoreSight debug port that combines a 5-pin JTAG-DP interface
DocID029918 Rev 1
Figure 16 shows the
AN4938