Debug Management; Introduction; Swj Debug Port (Serial Wire And Jtag); Pinout And Debug Port Pins - ST STM32F74 Series Getting Started

AN4661
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Debug management

5.1

Introduction

The host/target interface is the hardware equipment that connects the host to the application
board. This interface is made of three components: a hardware debug tool, a JTAG or SW
connector and a cable connecting the host to the debug tool.
connection of the host to the evaluation board.
5.2

SWJ debug port (serial wire and JTAG)

The core of the STM32F74xxx/STM32F75xxx integrates the Serial Wire / JTAG Debug Port
(SWJ-DP). It is an ARM
interface and a SW-DP (2-pin) interface.
•
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
•
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
For more details on the SWJ debug port refer to RM0385 SWJ debug port section (serial
wire and JTAG).
5.3

Pinout and debug port pins

The STM32F74xxx/STM32F75xxx devices are available in various packages with different
numbers of available pins. As a result, some functionality related to pin availability (TPIU
parallel output interface) may differ between packages.

Figure 16. Host to board connection

®
standard CoreSight debug port that combines a JTAG-DP (5-pin)
DocID027559 Rev 2
Debug management
Figure 16 shows the
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