Table 260. Jtag/Serial-Wire Debug Port Pins; Table 261. Single-Wire Trace Port Pins; Table 262. Debug Access Control Overview - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
JTMS=1
Test-Logic-
Reset
JTMS=0
JTMS=0
Run-Test/
Idle
The operation of the JTAG-DP is as follows:
When the TAPSM goes through the Capture-IR state, 0b0001 is transferred onto the
instruction register (IR) scan chain. The IR scan chain is connected between JTDI and
JTDO.
While the TAPSM is in the Shift-IR state, the IR scan chain shifts one bit for each rising
edge of JTCK. This means that, on the first tick:
When the TAPSM goes through the Update-IR state, the value scanned into the IR
scan chain is transferred into the instruction register.
When the TAPSM goes through the Capture-DR state, a value is transferred from one
of the data registers onto one of the DR scan chains, connected between JTDI and
JTDO.
The value held in the instruction register determines which data register and associated
DR scan chain are selected.
Figure 384. JTAG TAP state machine
JTMS=1
JTMS=1
JTMS=0
JTMS=1
JTMS=0
JTMS=1
JTMS=0
JTMS=1
JTMS=1
The LSB of the IR scan chain is output on JTDO.
Bit[n] of the IR scan chain is transferred to bit[n-1].
The value on JTDI is transferred to the MSB of the IR scan chain.
JTMS=1
Select-
DR-Scan
JTMS=0
Capture-
DR
Shift-DR
JTMS=0
JTMS=1
Exit1-DR
Pause-
DR
JTMS=0
Exit2-DR
Update-
DR
JTMS=0
RM0453 Rev 2
Debug support (DBG)
Select-
IR-Scan
JTMS=0
JTMS=1
Capture-
IR
JTMS=0
Shift-IR
JTMS=1
JTMS=0
Exit1-IR
JTMS=0
Pause-IR
JTMS=1
JTMS=0
JTMS=0
Exit2-IR
JTMS=1
Update-
IR
JTMS=1
JTMS=0
JTMS=1
JTMS=1
MSv60366V1
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