Cortex ® -M4 With Fpu Jedec-106 Id Code; Jtag Debug Port; Table 234. Jtag Debug Port Data Registers - ST STM32F423 Reference Manual

Debug support (DBG)
34.6.4 Cortex
The Arm
ROM table mapped on the internal PPB bus at address 0xE00F FFD0_0xE00F FFE0.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
34.7

JTAG debug port

A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex
Manual (TRM), for references, please see
IR(3:0)
1111
1110
1010
1292/1324
®
-M4 with FPU JEDEC-106 ID code
® ®
Cortex -M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4KB

Table 234. JTAG debug port data registers

Data register
BYPASS
[1 bit]
IDCODE ID CODE
[32 bits] 0x4BA0 0477 (Arm
Debug port access register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
DPACC
– When transferring data OUT:
[35 bits]
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to
®
-M4 with FPUr0p1 Technical Reference
Section 34.2: Reference Arm®
® ®
Cortex -M4 with FPU
Table 235 for a description of the A[3:2] bits
RM0430 Rev 8
documentation).
Details
r0p1
ID Code)
RM0430