Dma Requests - ST STM32F412 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
Timeout Error (TIMEOUT)
This section is relevant only when the SMBus feature is supported. Refer to
FMPI2C
A timeout error occurs for any of these conditions:
•
TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is
used to detect a SMBus timeout.
•
TIDLE=1 and both SDA and SCL remained high for the time defined in the TIMEOUTA
[11:0] bits: this is used to detect a bus idle condition.
•
Master cumulative clock low extend time reached the time defined in the
TIMEOUTB[11:0] bits (SMBus t
•
Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0]
bits (SMBus t
When a timeout violation is detected in master mode, a STOP condition is automatically
sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When a timeout error is detected, the TIMEOUT flag is set in the FMPI2C_ISR register, and
an interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register.
Alert (ALERT)
This section is relevant only when the SMBus feature is supported. Refer to
FMPI2C
The ALERT flag is set when the FMPI2C interface is configured as a Host (SMBHEN=1),
the alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA
pin. An interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register.
23.4.16

DMA requests

Transmission using DMA
DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit
in the FMPI2C_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see
register whenever the TXIS bit is set.
Only the data are transferred with DMA.
•
In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
704/1163
implementation.
parameter)
LOW:SEXT
implementation.
Section 9: Direct memory access controller
parameter)
LOW:MEXT
RM0402 Rev 6
Section 23.3:
Section 23.3:
(DMA)) to the FMPI2C_TXDR
RM0402