I2C Control Register 2 (I2C_Cr2) - ST STM32WL5 Series Reference Manual

RM0453
34.7.2

I2C control register 2 (I2C_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
HEAD1
NACK STOP START
rs rs rs
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 PECBYTE: Packet error checking byte
Note: Writing '0' to this bit has no effect.
Bit 25 AUTOEND: Automatic end mode (master mode)
Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
Bits 23:16 NBYTES[7:0]: Number of bytes
Note: Changing these bits when the START bit is set is not allowed.
28 27 26 25
PEC AUTOE
Res.
BYTE ND
rs rw
12 11 10 9
RD_
ADD10
0R WRN
rw rw rw rw
This bit is set by software, and cleared by hardware when the PEC is transferred, or when a
STOP condition or an Address matched is received, also when PE=0.
0: No PEC transfer.
1: PEC transmission/reception is requested
This bit has no effect when RELOAD is set.
This bit has no effect is slave mode when SBC=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Refer to Section 34.3: I2C
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR
flag is set when NBYTES data are transferred, stretching SCL low.
The number of bytes to be transmitted/received is programmed there. This field is don't care
in slave mode with SBC=0.
Inter-integrated circuit (I2C) interface
24 23 22
RE
LOAD
rw rw rw
8 7 6
rw rw rw
implementation.
RM0453 Rev 1
21 20 19 18
NBYTES[7:0]
rw rw rw rw
5 4 3 2
SADD[9:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
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