Detailed Explanation Of Registers For Input Capture - Fujitsu MB90420/5 (A) Series Hardware Manual

11.3.1 Detailed Explanation of Registers for Input Capture

Two types of input capture data registers are shown below:
• Input capture data register (IPCP0 to IPCP3)
• Input capture control register (IPCP)
n Input capture data register (IPCP0 to 3)
This register holds the value of the 16-bit free-run timer when an effective edge is detected of the
corresponding external pin input wave (Perform word access to this register. It is impossible to write to this
register).
Input capture data register (upper)
Address: ch0 000061
Address: ch1 000063
Address: ch2 000065
Address: ch3 000067
Input capture data register (lower)
Address: ch0 000060
Address: ch1 000062
Address: ch2 000064
Address: ch3 000066
n Input capture control status register (ICS01, ICS23)
Capture control register (upper)
Address: 00006A
H
Capture control register (lower)
Address: 000068
H
[bits 7, 6] ICP3, ICP2, ICP1, ICP0
These are input capture interrupt flags. When the effective edge of the external input pin is detected,
these bits are set to 1. When the interrupt enable bits (ICE3, ICE2, ICE1 and ICE0) are set, an interrupt
can be generated by detecting the effective edge. These bits are cleared by writing 0. Writing 1 has no
meaning. 1 can be read by the read-modify-instruction.
ICPn: Number of n corresponds to the channel number of input capture.
INPUT CAPTURE
bit 15 bit 14 bit 13
H
CP15 CP14 CP13
H
(R) (R)
H
(X) (X)
H
bit 7 bit 6 bit 5
H
CP07 CP06 CP05
H
(R) (R)
H
(X) (X)
H
bit 7 bit 6 bit 5
ICP3 ICP2 ICE3
(R/W) (R/W) (R/W)
(0) (0)
bit 7 bit 6 bit 5
ICP1 ICP0 ICE1
(R/W) (R/W) (R/W)
(0) (0)
0 Effective edge not detected
1 Effective edge detected
bit 12 bit 11
CP12 CP11
(R) (R) (R)
(X) (X) (X)
bit 4 bit 3
CP04 CP03
(R) (R) (R)
(X) (X) (X)
bit 4 bit 3
ICE2 EG31
(R/W) (R/W)
(0) (0) (0)
bit 4 bit 3
ICE0 EG11
(R/W) (R/W)
(0) (0) (0)
11-7
bit 10 bit 9 bit 8
CP10 CP09 CP08
(R) (R) (R)
(X) (X) (X)
bit 2 bit 1 bit 0
CP02 CP01 CP00
(R) (R) (R)
(X) (X) (X)
bit 2 bit 1 bit 0
EG30 EG21 EG20
(R/W) (R/W) (R/W)
(0) (0) (0)
bit 2 bit 1 bit 0
EG10 EG01 EG00
(R/W) (R/W) (R/W)
(0) (0) (0)
[Initial value]
IPCP0 to 3
← Read/write
← Initial value
IPCP0 to 3
← Read/write
← Initial value
ICS23
← Read/write
← Initial value
ICS01
← Read/write
← Initial value