External Transfer Requests; Table 2-5: External Transfer Request - Fujitsu FR Series Application Note

When the high priority interrupt occurs (NMI or interrupt priority higher than that specified by
LVL bits if HRCL register) during the DMAC transfer, the DMAC transfer gets temporarily
stopped by the hold request cancel request from NMI or by the peripheral. The
corresponding ISR starts getting executed. Now within this ISR if the corresponding interrupt
flag is cleared then DMAC transfer is restarted. In this case to continue suppressing the
DMAC transfer, the DMAH[3:0] bits of DMACR register should be incremented by 1 before
clearing the interrupt flag and it should be decremented by 1 before leaving the ISR. This is
how the DMAC transfer would be suppressed until the execution of ISR. In such case the
DMAC transfer would be continued before the execution of RETI instruction.
In case of nested interrupts the DMAC transfer would be only continued after the lowest
priority interrupt (interrupt with the lowest priority among the pending interrupt but priority
higher than that specified by LVL bits if HRCL register) finishes execution.

2.4.4 External Transfer Requests

Sr. Pin
Description
No Name
1 DREQ External Transfer
Request Input Pin
2 DACKX External Transfer
Request
Acknowledgement
Output Pin
3 DEOP DMA End Output
Pin
4 DEOTX External Transfer
Stop Pin
© Fujitsu Microelectronics Europe GmbH
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
External transfer request can be issued over
DREQ pin.
The configurable levels are low level or high level
and the configurable edges are rising edge or
falling edge.
It should be noted that the minimum width of the
signal appearing at DREQ should be 5 system
clock cycles.
This is an acknowledgement signal with reference
to DREQ. It indicates that the external transfer
with respect to the transfer request is performed
and usually being asserted during the external bus
access.
In the 2-cycle transfer it is asserted either while the
external source or while the external destination is
being accessed.
In the fly-by transfer it is continuous asserted since
the source as well as the destination is external.
Signal on this pin indicates that the DMAC transfer
is performed for specified number of times.
DEOP is asserted while the last data item of the
last block is being transferred
If the transfer source and destination is internal
then the DEOP is not asserted.
Using this pin the ongoing DMAC transfer can be
forcibly stopped.
If the transfer is stopped using this pin then the
DMAH[2:0] bits of the DMACB register would
transfer stop request. Interrupt may be generated if
it is enabled.
It should be noted that this pin shared with DEOP.
The minimum width of the signal appearing at
DEOTX pin should be 5 system clock cycles.

Table 2-5: External Transfer Request

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Functionality
MCU-AN-300059-E-V11