Hold Request Cancellation Request Level Setting Register (Hrcl) - Fujitsu FR60 Hardware Manual

CHAPTER 11 INTERRUPT CONTROLLER
11.2.2 Hold Request Cancellation Request Level Setting
Register (HRCL)
The hold request cancellation request level setting register (HRCL) is a level setting
register used to generate a hold request cancellation request.
■ Bit Configuration of Hold Request Cancellation Request Level Setting Register (HRCL)
Figure 11.2-3 shows the bit configuration of the hold request cancellation request level setting
register (HRCL).
Figure 11.2-3 Bit Configuration of the Hold Request Cancellation Request Level Setting Register (HRCL)
Address: 000045
■ Detailed Bit of Hold Request Cancellation Request Level Setting Register (HRCL)
The following describes the bit functions of the hold request cancellation request level setting
register (HRCL).
[bit7] MHALTI: DMA transfer disable by NMI request
This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets
this bit to "1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit the
same way it would be cleared in a normal interrupt routine.
[bit4 to bit0] LVL4 to LVL0: Interrupt level setting
These bits set the interrupt level used to issue a hold request cancellation request to the bus
master.
If an interrupt request with a higher level than the level specified in the HRCL register occurs,
issue a hold request cancellation request to the bus master.
The LVL4 bit is always "1". "0" cannot be written to it.
336
bit 7 6 5
- -
MHALTI
H
R/W
4 3 2 1
LVL4 LVL3 LVL2 LVL1
R R/W R/W R/W
0 Initial value
0--11111
LVL0
B
R/W