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CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.1 Overview of DTP/External Interrupt Unit
The DTP (Data Transfer Peripheral) unit is a peripheral control section located between
the peripheral units outside the device and the F
DMA request or interrupt requests from the external peripheral device and report such
2
MC-16LX CPU to start μDMAC, EI
requests to the F
■
Overview of DTP/external interrupt unit
For μDMAC or EI
external interrupt requests, it can be selected from four types: rising, falling edges, "H" and "L"
signals.
■
Block diagram of DTP/external interrupt unit
Figure 16.1-1 shows a block diagram of the DTP/external interrupt.
2
F
MC-16 bus
4
Interrupt/DTP enable register
4
Gate
4
8
■
Pin related to DTP/external interrupt
The pin related to the external interrupt pin has the IRQ0/IRQ1/IRQ2/IRQ3/IRQ4/IRQ5/IRQ6/
IRQ7 pins and functions as an input port. The IRQ0/IRQ1/IRQ2/IRQ3/IRQ4/IRQ5/IRQ6/IRQ7
pins function as the general-purpose I/O port (P80/IRQ0,P81/IRQ1,P82/IRQ2,P83/IRQ3,P84/
IRQ4,P85/IRQ5,P86/IRQ6,P87/IRQ7) and external interrupt input pin.
● Setting when using as IRQ0/IRQ1/IRQ2/IRQ3/IRQ4/IRQ5/IRQ6/IRQ7 pins
When the P80/IRQ0,P81/IRQ1,P82/IRQ2,P83/IRQ3,P84/IRQ4,P85/IRQ5,P86/IRQ6,P87/IRQ7
pins are used as an input pin, be sure to set the port direction register to the input port (DDR8:
bit0 to 7 → "0").
342
2
OS, the request level can be selected from two types, "H" and "L". For
Figure 16.1-1 Block diagram of DTP/external interrupt unit
Source F/F
Interrupt/DTP source register
Request level setting register
2
MC-16LX CPU. It is used to receive
2
OS, or interrupt handling.
Edge detection circuit
4
Request input
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