Figure 3.8.4A External Bus Operation (Bus Cycle) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.8 Memory Access Modes
3.8.4 External Bus Operation
This section shows the operation of the external bus pins when accessing an external
area in external bus mode. The section also gives an example of connecting external
memory and peripheral functions.
n External Bus Operation
The address of the external memory or peripheral function accessed using the external bus pins
is specified by the address data output to the address pins (A08 to A15) and address/data pins
(AD0 to AD7). As input and output of the lower 8 bits of the address are multiplexed in the time
domain with the data bus, provide an external circuit to latch the address data on the falling
edge of the address latch enable signal output from the ALE pin.
Reading is synchronized with the read strobe signal output from the RD pin and the read data is
applied to the data pins.
Writing is synchronized with the write strobe signal output from the WR pin and completes when
the data output on the data pins is read by the external memory or others. The buffer control
output (BUFC) signal is used when an external data bus buffer is present. The signal controls
the data buffer I/O direction. Using the signal allows buffer I/O control to be performed easily.
Figure 3.8.4a shows the external bus operation (bus cycle).
Check: If the ready function is not used in external bus mode, an external pull-up must be provided for the
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CHAPTER 3 CPU
CLK
ALE
A08
Upper address
to A15
AD0
Lower
to AD7
address
RD
WR
BUFC

Figure 3.8.4a External Bus Operation (Bus Cycle)

RDY pin.
Data read Data write
Upper address
Read Lower
data address
Write data
MB89620 series