Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr); Rcc Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F205 series Reference Manual

RM0033
5.3.12

RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)

Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:1 Reserved, always read as 0.
Bit 0 FSMCEN: Flexible static memory controller module clock enable
Set and cleared by software.
0: FSMC module clock disabled
1: FSMC module clock enabled
5.3.13

RCC APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
DAC PWR
EN
Reserved
rw
15 14 13
SPI3 SPI2
EN EN
Reserved
rw rw
Bits 31:30 Reserved, always read as 0.
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 Reserved, always read as 0.
Bit 26 CAN2EN: CAN 2 clock enable
Set and cleared by software.
0: CAN 2 clock disabled
1: CAN 2 clock enabled
28 27 26 25
12 11 10 9
28 27 26 25
CAN2 CAN1
Reser-
EN EN EN
ved
rw rw rw
12 11 10 9
WWDG
EN
Reserved
rw
24 23 22
Reserved
8 7 6
Reserved
24 23 22 21
I2C3 I2C2 I2C1
Reser-
EN EN EN
ved
rw rw
8 7 6
TIM14 TIM13 TIM12 TIM7
EN EN EN EN
rw rw rw
RM0033 Rev 8
Reset and clock control (RCC)
21 20 19 18
5 4 3 2
20 19 18
UART5 UART4 USART3
EN EN EN
rw rw rw rw
5 4 3 2
TIM6 TIM5 TIM4
EN EN EN
rw rw rw rw
17 16
1 0
FSMCEN
rw
17 16
USART2
Reser-
EN
ved
rw
1 0
TIM3 TIM2
EN EN
rw rw
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