Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr); Rcc Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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Reset and clock control (RCC)

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSEN: USB OTG FS clock enable

This bit is set and cleared by software.

0: USB OTG FS clock disabled

1: USB OTG FS clock enabled

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 DCMIEN: Camera interface enable

This bit is set and cleared by software.

0: Camera interface clock disabled

1: Camera interface clock enabled

RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)

Address offset: 0x38

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 QSPIEN: QUADSPI memory controller module clock enable

This bit is set and cleared by software.

0: QUADSPI module clock disabled

1: QUADSPI module clock enabled

Bit 0 FMCEN: Flexible memory controller module clock enable

This bit is set and cleared by software.

0: FMC module clock disabled

1: FMC module clock enabled

Address offset: 0x40

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

RM0390 Rev 4

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