Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr); Rcc Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus
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RM0430
6.3.14

RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)

Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIEN: QUADSPI memory controller module clock enable
Set and cleared by software.
0: QUADSPI clock disabled
1: QUADSPI clock enabled
Bit 0 FSMCEN: Flexible memory controller module clock enable
Set and cleared by software.
0: FSMC module clock disabled
1: FSMC module clock enabled
6.3.15

RCC APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x40
Reset value: 0x0000 0400
Access: no wait state, word, half-word and byte access.
31
30
29
28
PWR
UART8
UART7
DAC
EN
EN
EN
EN
rw
rw
rw
rw
15
14
13
12
SPI3
SPI2
Res.
Res.
EN
EN
rw
rw
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
27
26
25
CAN1
CAN3
CAN2
EN
EN
EN
rw
rw
rw
11
10
9
WWDG
RTCAPB
LPTIMER1
EN
EN
EN
rw
rw
rw
Reset and clock control (RCC) for STM32F413/423
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
I2CFMP1
I2C3
I2C2
EN
EN
EN
rw
rw
rw
8
7
6
TIM14
TIM13
TIM12
EN
EN
EN
rw
rw
rw
RM0430 Rev 8
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
21
20
19
18
I2C1
USART3
UART4
UART4
EN
EN
EN
EN
rw
rw
rw
rw
5
4
3
2
TIM5
TIM4
TIM7
TIM6
EN
EN
EN
EN
rw
rw
rw
rw
17
16
Res.
Res.
1
0
QSPI
FSMC
EN
EN
rw
rw
17
16
USART2
Res.
EN
rw
1
0
TIM3
TIM2
EN
EN
rw
rw
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