Rcc Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F410 Reference Manual

RM0401
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
5.3.9

RCC APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
DAC PWR
Res. Res.
EN
rw
15 14 13
SPI3 SPI2
Res. Res.
EN EN
rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEB: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 I2C4EN: I2C4 clock enable
Set and cleared by software.
0: I2C4 clock disabled
1: I2C4 clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bits 20:18 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
EN
rw
12 11 10 9
WWDG RTCAPB LPTIM1
EN EN EN
rw rw rw
24 23 22 21
I2C4 I2C2 I2C1
Res.
EN EN EN
rw rw rw
8 7 6
Res. Res. Res. Res.
RM0401 Rev 3
Reset and clock control (RCC)
20 19 18
Res. Res. Res.
5 4 3 2
TIM6 TIM5
Res.
EN EN
rw rw
17 16
USART2
Res.
EN
rw
1 0
Res. Res.
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