Mechanism To Select The Jtag-Dp Or The Sw-Dp; Pinout And Debug Port Pins; Swj Debug Port Pins; Flexible Swj-Dp Pin Assignment - ST STM32F100 Series Reference Manual

Debug support (DBG)
25.3.1

Mechanism to select the JTAG-DP or the SW-DP

By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG
sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the
JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only
the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted
first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
25.4

Pinout and debug port pins

The STM32F100xx MCUs are available in various packages with different numbers of
available pins. As a result, some functionality (ETM) related to pin availability may differ
between packages.
25.4.1

SWJ debug port pins

Five pins are used as outputs from the STM32F100xx for the SWJ-DP as alternate functions
of general-purpose I/Os. These pins are available on all packages.
SWJ-DP pin name
Type
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
25.4.2

Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32F100xx MCU implements the
register (AFIO_MAPR)
releases the associated pins for General Purpose IOs usage. This register is mapped on an
APB bridge connected to the Cortex
by the user software program and not the debugger host.
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Table 145. SWJ debug port pins

JTAG debug port
Description
I JTAG Test Mode Selection
I JTAG Test Clock
I JTAG Test Data Input
O JTAG Test Data Output
I JTAG Test nReset
register to disable some part or all of the SWJ-DP port and so
SW debug port
Type Debug assignment
IO Serial Wire Data Input/Output
I Serial Wire Clock
- -
TRACESWO if async trace is
-
enabled
- -
AF remap and debug I/O configuration
®
-M3 System Bus. Programming of this register is done
RM0041 Rev 6
RM0041
Pin
assignment
PA13
PA14
PA15
PB3
PB4