Error Conditions; Figure 241. Method 2: Transfer Sequence Diagram For Master Receiver When N=1 - ST STM32F100 Series Reference Manual

Inter-integrated circuit (I2C) interface

Figure 241. Method 2: transfer sequence diagram for master receiver when N=1

7- bit master receiver
10- bit master receiver
S
Legend: S = Start, S
EVx = Event (with interrupt if ITEVFEN = 1)
EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.
EV6: ADDR =1, cleared by reading SR1 resister followed by reading SR2 register.
EV6_3: ADDR = 1, program ACK = 0, clear ADDR by reading SR1 register followed by reading SR2 register, program
STOP =1 just after ADDR is cleared.
Note: The EV6_3 software sequence must complete before the current byte end of transfer.
EV7: RxNE =1, cleared by reading DR register.
EV9: ADD10= 1, cleared by reading SR1 register followed by writing DR register.
.
1. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
22.3.4

Error conditions

The following are the error conditions which may cause communication to fail.
Bus error (BERR)
This error occurs when the I
an address or a data transfer. In this case:
•
the BERR bit is set and an interrupt is generated if the ITERREN bit is set
• in Slave mode: data are discarded and the lines are released by hardware:
–
–
•
In Master mode: the lines are not released and the state of the current transmission is
not affected. It is up to the software to abort or not the current transmission
Acknowledge failure (AF)
This error occurs when the interface detects a nonacknowledge bit. In this case:
•
the AF bit is set and an interrupt is generated if the ITERREN bit is set
•
a transmitter which receives a NACK must reset the communication:
–
–
578/709
S Address A Data1
EV5 EV6_3
Header A Address
EV5 EV9
= Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge,
r
2
C interface detects an external Stop or Start condition during
in case of a misplaced Start, the slave considers it is a restart and waits for an
address, or a Stop condition
in case of a misplaced Stop, the slave behaves like for a Stop condition and the
lines are released by hardware
If Slave: lines are released by hardware
If Master: a Stop or repeated Start condition must be generated by software
NA P
EV7
A
EV6
S Header A
r
EV5
RM0041 Rev 6
Data1 NA P
EV6_3 EV7
RM0041