Error Conditions; Figure 237. Bus Transfer Diagrams For Smbus Master Receiver - ST STM32F412 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP)
NBYTES
INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC
Example SMBus master receiver 2 bytes + PEC, software end mode (RESTART)
INIT
NBYTES
xx
INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program Slave address, program NBYTES = N, set START
23.4.15

Error conditions

The following errors are the error conditions which may cause communication to fail.
Bus error (BERR)
A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a
SDA edge occurs while SCL is high.
The bus error flag is set only if the FMPI2C is involved in the transfer as master or
addressed slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the FMPI2C enters
address recognition state like for a correct START condition.
702/1163

Figure 237. Bus transfer diagrams for SMBus master receiver

data1
Address A
S
INIT
xx 3
RXNE
Address A data1 A
S
EV1
3
RXNE RXNE
PEC
data2
A A
E V 1 EV2
RXNE RXNE
data2 A PEC
NA
EV2 EV3
RM0402 Rev 6
RXNE
legend:
NA P
E V 3
legend:
TC
Restart Address
EV4
N
RM0402
transmission
reception
SCL stretch
transmission
reception
SCL stretch
MS19872V2