Dac Channel1 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L1); Dac Channel1 8-Bit Right Aligned Data Holding Register (Dac_Dhr8R1) - ST STM32F446 Series Reference Manual

RM0390
14.5.4

DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
14.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
27 26 25
Res. Res. Res.
11 10 9
DACC1DHR[11:0]
rw rw rw rw
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res. Res.
8 7 6
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res.
rw rw
RM0390 Rev 4
Digital-to-analog converter (DAC)
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res.
rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
DACC1DHR[7:0]
rw rw rw rw
17 16
Res. Res.
1 0
Res. Res.
17 16
Res. Res.
1 0
rw rw
417/1328
422