Port Bit Reset Register (Gpiox_Brr) (X=A..g; Port Configuration Lock Register (Gpiox_Lckr) (X=A..g - ST STM32F100 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
7.2.6

Port bit reset register (GPIOx_BRR) (x=A..G)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
15 14 13
BR15 BR14 BR13 BR12
w w w
Bits 31:16
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
7.2.7

Port configuration lock register (GPIOx_LCKR) (x=A..G)

This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
15 14 13
LCK15 LCK14 LCK13 LCK12
rw rw rw
116/709
28 27 26 25
12 11 10 9
BR11 BR10 BR9
w w w w
Reserved
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
28 27 26 25
12 11 10 9
LCK11 LCK10 LCK9
rw rw rw rw
24 23 22
Reserved
8 7 6
BR8 BR7 BR6
w w w
24 23 22
Reserved
8 7 6
LCK8 LCK7 LCK6
rw rw rw
RM0041 Rev 6
21 20 19 18
5 4 3 2
BR5 BR4 BR3 BR2
w w w w
21 20 19 18
5 4 3 2
LCK5 LCK4 LCK3 LCK2
rw rw rw rw
RM0041
17 16
1 0
BR1 BR0
w w
17 16
LCKK
rw
1 0
LCK1 LCK0
rw rw