Dsp Dma Controller Features - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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DSP DMA Controller Features

The DSP DMA controller has the following features:

Operation independent of the MPU.

Four standard ports, one for each data resource: DARAM, SARAM,

external memory via EMIF, and peripherals via the shared TIPB bridge.

An auxiliary port to enable certain transfers between the MPUI and

Six logical channels, which allow the DMA controller to keep track of the

context of six independent block transfers plus a seventh logical channel

for MPUI transfers.

Bits for assigning each channel a low priority or a high priority. For details,

see Section 4.4, Service Chain.

Event synchronization. DMA transfers in each channel can be made

dependent on the occurrence of selected events. For details, see Section

4.13, Synchronizing Channel Activity.

An interrupt for each channel. Each channel can send an interrupt to the

CPU on completion of certain operational events (see Section 4.16,

Monitoring Channel Activity).

Software-selectable options for updating addresses for the sources and

destinations of data transfers.

The DMA EMIF does not have 8-bit read support. Internally, 8-bit

DMA transfers from external to internal memory convert into 16-bit

element reads. The appropriate byte is fetched from this read and

placed in internal memory.

The DSP DMA controller performs data transfers between the following

source and destination ports:

Single-access RAM

Dual-access RAM

External memory

TI peripheral bus

MPUI interface

Direct Memory Access (DMA) Support

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