Ultralow-Power Device; Ulpd Features - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Ultralow-Power Device

This document describes power management in the OMAP5912 multimedia

The ultralow-power device (ULPD) generates and manages clocks and reset

signals to OMAP3.2 and to some peripherals. It controls chip-level

power-down modes and handles chip-level wake-up events. In deep sleep

mode, this module is still active to monitor wake-up events.

This chapter describes the ULPD module and outline architecture. For further

information on clock sources and clock and reset architecture, see Chapter 4

and Chapter 5.

The ULPD has the following features:

Performs transitions among power modes (awake, big sleep, and deep

Handles idle/wake-up handshake with OMAP3.2

Monitors wake-up events

Controls system clock input sources for several possible configurations

(oscillator/external clocks)

Performs calibration of the 32-kHz oscillator

Manages the clocks and resets distributed to OMAP3.2 and to some

Handles the power-up sequence

Controls an on-chip PLL that generates a 96-MHz clock (for 48-MHz

peripheral clocks)

Is controlled by the MPU for set up and configuration

Manages the sleep signal of an embedded LDO used to regulate the

supply voltage for OMAP3.2 digital phase locked loop (DPLL) and the

system clock oscillator

Power Management

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