Reset Context; Overflow/Reset Generation; Triggering New Reload - Texas Instruments OMAP5912 Reference Manual

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Reset Context

32-Bit Watchdog- General Functional Overview

Load register

After reset release, the 32-bit watchdog is on. To get the reset values, software

must read the PTV field of WCLR and the 32-bit register to catch the static

configuration of the module.

When the watchdog counter register (WTCR) reaches overflow, an active-low

pulse is generated to the ULPD. After reset generation, the counter is

automatically reloaded with the watchdog load register (WLDR) and the

prescaler counter is reset. The prescaler ratio remains unchanged. Then, after

the reset pulse has been generated, the prescaler counter and timer counter

are incremented again. Figure 2 shows the 32-bit watchdog functional

Trg register

Counter register

To reload the timer counter and reset the prescaler counter values without

reaching overflow, a reload command can be executed by accessing the

watchdog trigger register (WTGR) using a specific reload sequence.

The specific reload sequence is performed when the written value on the

watchdog trigger register (WTGR) is different from its previous value. In this

case, reload is executed in the same way as overflow autoreload, without a

reset pulse generation. The timer is loaded with the watchdog load register

(WLDR) value and the prescaler counter is reset.

32-Bit Watchdog Timer General Overview

reset pulse is

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