Functional Description; System Dma Controller Simplified Block Diagram - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Functional Description

Direct Memory Access (DMA) Support

Port control bus

System DMA controller

This section describes the system DMA capabilities and programming.

The configuration of the system DMA logical channel registers can be done

in any order with the exception of the enable bit in the channel control register,

DMA_CCR. This bit enables all logical channel types, so this must be the last

thing done when configuring a logical channel (LCh). During the time an LCh

is enabled it is not allowed to change its configuration registers, which causes

undefined effects. All global system DMA configuration registers must be

changed before any LChs are enabled; if not, it undefined effects result.

The dedicated LCD channel has some additional features and different

channel behavior compared to the generic channels. For more details, see

section 3.2.1, Display Logical Channel. Some channel features and behavior

are common to both generic and LCD channels; this section describes them

and indicates which are supported by the LCD channel.

TIPB config port

Channel control

Memory interface

Logical channel arbitration

Logical channel interleaving

Logical channel prefetch

Logical channel linking control

Memory access control

Channel text

Channel state

Clock control

Idle control

MISC control

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