Operating System Timer; Countdown Operation - Texas Instruments OMAP5912 Reference Manual

6

Operating System Timer

Figure 11. OS Timer
6.1

Countdown Operation

SPRU759B
The operating system (OS) timer is a 24-bit timer with the 32-kHz clock.
Figure 11 shows the operating system timer.
A/cs
Address/CS decoding
dout
din
IRQ
Canonical operation of the OS timer works as follows:
1) The host MPU writes the counter initial value to the tick value register
(TICK_VALUE_REG), where, by default, all bits are set to 1.
2) The host MPU sets the timer reload bit (TRB) inside the timer control
register (TIMER_CTRL_REG).
3) MPU polls the TRB bit. When it is cleared, the timer internal counter has
been loaded with the the tick value register (TICK_VALUE_REG) value.
4) MPU then launches the timer by setting the timer start stop bit (TSS) inside
the timer control register (TIMER_CTRL_REG). The timer starts to count
down to zero and generates a negative edge-sensitive interrupt (low level
15-µs-wide pulse) to the interrupt controller.
5) On the next cycle, the counter is reloaded from the tick value register
(TICK_VALUE_REG) and then starts to down count again, unless the ARL
bit of the timer control register (TIMER_CTRL_REG) is low: one-shot
mode.
Tick value register
)
(TICK_VALUE_REG
Timer control register
(TIMER_CTRL_REG)
Operating System Timer
24-bits counter
Comparator
Timers 55