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System DMA
3
System DMA
28
Direct Memory Access (DMA) Support
The system DMA is designed to off-load the block data transfer function from
the MPU.
The OMAP 3.2 system DMA controller consists of:
Sixteen logical channels plus one LCD logical channel
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Seven physical ports plus one for configuration
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Three physical channels plus one LCD dedicated physical channel
-
The ports are connected to the OCP-T1 and OCP-T2 targets, the external
memory, the TIPB bridge, the MPUI, and one dedicated port connected to an
LCD controller. The system DMA controller can be controlled via the MPU
private TIPB or by an external host via the OCP-I port.
The system DMA controller is designed for low-power operation. It is
partitioned into several clock domains where each clock domain is enabled
only when it is used. All clocks are disabled when no DMA transfers are active.
Five different logical channels types are supported; each one represents a
specific feature set.
LCh-2D for memory to memory transfers, 1D and 2D
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LCh-P for peripheral transfers
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LCh-PD for peripheral transfers on a dedicated channel
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LCh-G for graphical transfers/operations
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LCh-D for display transfers
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The features available are:
Support for up to four address modes:
-
Constant
J
Post-incremented mode
J
Single-indexed
J
Double-indexed
J
Different indexing for source-respective destination
-
Logical channel chaining
-
Software enabling
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Hardware enabling− 31 DMA request lines available
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Logical channel interleaving
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Logical channel preemption
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SPRU755B
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