Data Alignment - Texas Instruments OMAP5912 Reference Manual

Data Alignment

SPRU755B
An element (data type) can be:
8-bit scalar data, s8 (which means that ES = 1)
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16-bit scalar data, s16 (which means that ES = 2)
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32-bit scalar data, s32 (which means that ES = 4)
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To set up a channel for a transfer, the software must program two addressing
modes:
The source addressing mode, source index size
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The destination addressing mode, destination index size
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Both address modes for source and destination are independent. For
example, to transfer data from TIPB port to internal memory, the
source-addressing mode can be constant and the destination mode can be
post-incremented. However, the number of frames, the number of elements,
and the element size are the same for both source and destination.
Note:
The channel source and destination start addresses are configured in
separate registers: DMA_CSSA_L/U and DMA_CDSA_L/U respectively.
Frame index and element index are configured in separate registers for both
source and destination: DMA_CSFI and DMA_CSEI, respectively, for
source, and DMA_CDFI and DMA_CDEI, respectively, for destination.
During a transfer, the start address and all the addresses computed by the
DMA must be aligned on the type of data transferred (data type):
If the data type is s8 (8-bit scalar data), then addresses can have any
-
value.
If the data type is s16 (16-bit scalar data), then addresses must be aligned
-
on 16-bit word boundary (the lowest bit of the address always 0).
If the data type is s32 (32-bit scalar data), then addresses must be aligned
-
on 32-bit word boundary (the two lowest bit of the address always 00).
If it is 4x32 burst access with s32 (32-bit scalar data), then addresses must
-
be aligned on burst boundary (the four lowest bit of the address always
0000).
If frame index is used, it must always produce addresses aligned on data
-
type boundary.
If element index is used, it must always produce addresses aligned on
-
data type boundary.
Transfer block size must be aligned on the data type boundary.
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Failure to follow these rules generates undefined operation due to wrong
endianism switching.
Direct Memory Access (DMA) Support
System DMA
45