Memory Space Issues; Dma Operation In Power-Down Mode - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Memory Space Issues

Direct Memory Access (DMA) Support

If the time-out counter reaches its threshold before the request is

acknowledged, the request is discarded and an error is reported in the

DMA channel by setting the relevant bit in DMA_CSR (channel status

For a channel, all of the sources are combined to generate one interrupt. When

an interrupt is issued by a channel, its status register (DMA_CSR) is set to

record the interrupt cause. The processor interrupt service routine (ISR) can

read this channel status register to determine the source of the interrupt. The

status bits are automatically cleared after they are read.

To set up a transfer, the software specifies:

A source port with an address that must hit in the source port memory

A destination port with an address that must hit in the destination port

memory space.

If the software specifies a port with an address that does not hit this port

memory space (example: source port = SARAM with a DARAM start address

specified), the transfer goes on and memory can be corrupted. No address

space check is performed by the DMA and outside the DMA.

Programmers must ensure coherency between the source port and source

start address, and between the destination port and destination start address.

The DMA has five clock domains per channel and one per port.

The DMA stops all clocks in a channel when the channel is inactive, and

partially stops the clocks (14% of the logic remains active) when the channel

is active but blocked (waiting for DMA request or wait states during transfer).

The clock in a port is stopped when a channel does not use this port or when

it is blocked (because of wait states).

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