Data Count (Dcount); Transmit/Receive Fifo Data Value (Data) - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture
Hide thumbs Also See for OMAP5912:
Table of Contents

Advertisement

I2C Multimaster Peripheral

Data Count (DCOUNT)

Table 26. Data Access Register(I2C_DATA)
Bit
Name
15:0
DATA

Transmit/Receive FIFO Data Value (DATA)

76
Serial Interfaces
Master modes only (receive or transmit).
This 16-bit countdown counter decrements by 1 for every byte received or
sent. A write initializes DCOUNT to a saved initial value. A read returns the
number of bytes that are yet to be received or sent. A read into DCOUNT
returns the initial value only before a start condition and after a stop condition.
When DCOUNT reaches 0, the core generates a stop condition if a stop
condition was specified (I2C_CON:STP = 1), and the ARDY status flag is set
to 1 in the I2C_STAT register.
If I2C_CON:STP = 0, then the I
0. The LH can then reprogram DCOUNT to a new value and resume sending
or receiving data with a new start condition (restart). This process repeats until
the LH sets the STP to 1 in the I2C_CON register.
The ARDY flag is set each time DCOUNT reaches 0 and DCOUNT is reloaded
to its initial value.
In slave mode (receive or transmit), DCOUNT is not used.
0x0: Data counter = 65536 bytes (2
0x1: Data counter = 1 bytes
↓ ↓
0xFFFF: Data counter = 65535 bytes (2
DCOUNT value after reset is 0x0000.
Description
Transmit/Receive FIFO data
This register is the entry point for the local host to read data from or write data
to the FIFO buffer. The FIFO size is 2 x 16 bits (4 bytes). Bytes within a word
are stored and read in little-endian format (I2C_CON:BE = 0) or big-endian
format (I2C_CON:BE = 1).
When read, this register contains the received I
This register must be accessed 16-bit-wise by the LH. In the case of an odd
number of bytes received to read, the upper byte (with I2C_CON.BE = 0) or
the lower byte (with I2C_CON.BE = 1) of the last access always reads as 0x00.
The LH must check the SBD status bit in I2C_STAT register in order to flush
this null byte.
2
C asserts SCL = 0 when DCOUNT reaches
16
)
16
−1)
2
C data packet (1 or 2 bytes).
SPRU760B

Advertisement

Table of Contents
loading

Table of Contents