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Texas Instruments MSP430x1xx User Manual

Texas Instruments MSP430x1xx User Manual

Texas instruments modules and peripherals user's guide

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MSP430x1xx Family

User's Guide

2005

Mixed Signal Products

SLAU049E

Table of Contents

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Page 1 MSP430x1xx Family User’s Guide 2005 Mixed Signal Products SLAU049E...
Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
Page 3: Read This First
About This Manual This manual discusses modules and peripherals of the MSP430x1xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family.
Page 4 Glossary Glossary ACLK Auxiliary Clock Analog-to-Digital Converter Brown-Out Reset Bootstrap Loader Central Processing Unit Digital-to-Analog Converter Digitally Controlled Oscillator See Basic Clock Module Destination Frequency Locked Loop General Interrupt Enable INT(N/2) Integer portion of N/2 Input/Output Interrupt Service Routine Least-Significant Bit Least-Significant Digit Low-Power Mode Memory Address Bus...
Page 5 Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition −0,−1 −(0),−(1) Condition after POR Bit Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0...
Page 7: Table Of Contents
Introduction ..............Architecture .
Page 8 Contents RISC 16-Bit CPU ..............CPU Introduction .
Page 9 Supply Voltage Supervisor ............SVS Introduction .
Page 10 Contents 10 Watchdog Timer ..............10.1 Watchdog Timer Introduction 10.2 Watchdog Timer Operation 10.2.1 Watchdog Timer Counter...
Page 11 14 USART Peripheral Interface, SPI Mode 14.1 USART Introduction: SPI Mode 14.2 USART Operation: SPI Mode 14.2.1 USART Initialization and Reset 14.2.2 Master Mode ............14.2.3 Slave Mode .
Page 12 Contents 18 ADC10 ............... . . 18.1 ADC10 Introduction .
Page 13: Introduction
This chapter describes the architecture of the MSP430. Topic Architecture ..........Flexible Clock System .
Page 14: Architecture
(MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x1xx family include: Ultralow-power architecture extends battery life 0.1-µA RAM retention 0.8-µA real-time clock mode...
Page 15: Embedded Emulation
Figure 1−1. MSP430 Architecture Clock ACLK Flash/ System SMCLK MCLK MAB 16-Bit RISC CPU 16-Bit MDB 16-Bit JTAG ACLK SMCLK Watchdog 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: Unobtrusive development and debug with full-speed execution, breakpoints, and single-steps in an application are supported.
Page 16: Address Space
Address Space 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words.
Page 17: Peripheral Modules
1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0. The address space from 010h to 0FFh is reserved for 8-bit peripheral modules.
Page 18 Introduction...
Page 19: System Resets, Interrupts, And Operating Modes
System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x1xx system resets, interrupts, and operating modes. Topic System Reset and Initialization Interrupts ........... .
Page 20: System Reset And Initialization
System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated.
Page 21: Power-On Reset (Por)
2.1.1 Power-On Reset (POR) When the V until V has risen above the V supply provides a fast rise time the POR delay, t active time on the POR signal to allow the MSP430 to initialize. If power to the MSP430 is cycled, the supply voltage V to ensure that another POR signal occurs when V does not fall below V and power-up conditions do not set correctly.
Page 22: Brownout Reset (Bor)
System Reset and Initialization 2.1.2 Brownout Reset (BOR) Some devices have a brownout reset circuit (see device-specific datasheet) that replaces the POR detect and POR delay circuits. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the V device by triggering a POR signal when power is applied or removed.
Page 23: Device Initial Conditions After System Reset
2.1.3 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: The RST/NMI pin is configured in the reset mode. I/O pins are switched to input mode as described in the Digital I/O chapter. Other peripheral modules and registers are initialized as described in their respective chapters in this manual.
Page 24: Interrupts
System Reset and Initialization 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2−4. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously.
Page 25: Non)-Maskable Interrupts (Nmi)
2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (NMIIE, ACCVIE, OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are automatically reset.
Page 26 System Reset and Initialization Figure 2−5. Block Diagram of (Non)-Maskable Interrupt Sources ACCV ACCVIFG FCTL1.1 ACCVIE IE1.5 Clear RST/NMI NMIIFG IFG1.4 Clear NMIIE IE1.4 Clear OSCFault OFIFG IFG1.1 OFIE IE1.1 Clear NMI_IRQA IRQA: Interrupt Request Accepted System Resets, Interrupts, and Operating Modes Flash Module KEYV System Reset...
Page 27 Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs. The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit. The ACCVIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by a flash access violation.
Page 28: Maskable Interrupts
System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2−6.
Page 29 Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual. 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)-maskable interrupts to be requested.
Page 30 System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction: (return from an interrupt service routine) RETI The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2−8. 1) The SR with all previous settings pops from the stack.
Page 31: Interrupt Vectors
2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h as described in Table 2−1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine.
Page 32: Operating Modes
Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2−10. The operating modes take into account three different needs: Ultralow-power Speed and data throughput Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2−9.
Page 33 Figure 2−10. MSP430x1xx Operating Modes For Basic Clock System Time Expired, Overflow WDTIFG = 1 WDTIFG = 1 WDT Active, Security Key Violation CPUOFF = 1 SCG0 = 0 SCG1 = 0 LPM0 CPU Off, MCLK Off, SMCLK On, ACLK On...
Page 34: Entering And Exiting Low-Power Modes
Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: Enter interrupt service routine: The PC and SR are stored on the stack The CPUOFF, SCG1, and OSCOFF bits are automatically reset Options for returning from the interrupt service routine: The original SR is popped from the stack, restoring the previous operating mode.
Page 35: Principles For Low-Power Applications
2.4 Principles for Low Power Applications Often, the most important factor for reducing power consumption is using the MSP430’s clock system to maximize the time in LPM3. LPM3 power consumption is less than 2 µA typical with both a real-time clock function and all interrupts active.
Page 36 2-18 System Resets, Interrupts, and Operating Modes...
Page 37: Risc 16-Bit Cpu
This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic CPU Introduction ..........CPU Registers .
Page 38: Cpu Introduction
CPU Introduction 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: RISC architecture with 27 instructions and 7 addressing modes.
Page 39 Figure 3−1. CPU Block Diagram MDB − Memory Data Bus Zero, Z Carry, C Overflow, V Negative, N Memory Address Bus − MAB R0/PC Program Counter R1/SP Stack Pointer R2/SR/CG1 Status R3/CG2 Constant Generator General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose...
Page 40: Cpu Registers
CPU Registers 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed.
Page 41: Stack Pointer (Sp)
3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes.
Page 42: Status Register (Sr)
CPU Registers 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remain- ing combinations of addressing modes are used to support the constant gen- erator.
Page 43: Constant Generator Registers Cg1 And Cg2
3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in Table 3−2. Table 3−2.
Page 44: General−Purpose Registers R4 - R15
CPU Registers 3.2.5 General−Purpose Registers R4 - R15 The twelve registers, R4−R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values and can be accessed with byte or word instructions as shown in Figure 3−7. Figure 3−7.
Page 45: Addressing Modes
3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 3−3 describe the contents of the As (source) and Ad (destination) mode bits. Table 3−3.
Page 46: Register Mode
Addressing Modes 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Length: Operation: Comment: Example: Before: 0A023h 0FA15h Note: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result.
Page 47: Indexed Mode
3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Length: Operation: Comment: Example: Before: Address Space 0FF16h 00006h 0FF14h 00002h 0FF12h 04596h 01094h 0xxxxh 01092h 05555h 0xxxxh 01090h 01084h 0xxxxh 01082h 01234h 0xxxxh 01080h Assembler Code Content of ROM...
Page 48: Symbolic Mode
Addressing Modes 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Length: Operation: Comment: Example: Before: Address Space 0FF16h 0FF14h 0F102h 0FF12h 0F018h 0F016h 0F014h 01116h 01114h 05555h 01112h 3-12 RISC 16-Bit CPU Assembler Code Content of ROM MOV EDE,TONI...
Page 49: Absolute Mode
3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Length: Operation: Comment: Example: Before: 0FF16h 0FF14h 0FF12h 0F018h 0F016h 0F014h 01116h 01114h 01112h This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address.
Page 50: Indirect Register Mode
Addressing Modes 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Length: Operation: Comment: Example: Before: Address Space 0xxxxh 0FF16h 0000h 0FF14h 04AEBh 0FF12h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0xxxxh 0FA30h 002A8h 0xxh 002A7h...
Page 51: Indirect Autoincrement Mode
3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Length: Operation: Comment: Example: Before: Address Space 0xxxxh 0FF18h 0FF16h 00000h 0FF14h 04ABBh 0FF12h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0xxxxh 0FA30h 010AAh 0xxxxh 010A8h...
Page 52: Immediate Mode
Addressing Modes 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10.Immediate Mode Description Length: Operation: Comment: Example: Before: Address Space 0FF16h 0FF14h 0FF12h 010AAh 010A8h 010A6h 3-16 RISC 16-Bit CPU Assembler Code Content of ROM #45h,TONI MOV @PC+,X(PC) X = TONI −...
Page 53: Instruction Set
3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction.
Page 54: Double-Operand (Format I) Instructions
Instruction Set 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format Op-code Table 3−11 lists and describes the double operand instructions. Table 3−11. Double Operand Instructions Mnemonic S-Reg, Mnemonic S-Reg, MOV(.B) ADD(.B) ADDC(.B) SUB(.B)
Page 55: Single-Operand (Format Ii) Instructions
3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format Table 3−12 lists and describes the single operand instructions. Table 3−12.Single Operand Instructions Mnemonic RRC(.B) RRA(.B) PUSH(.B) SWPB CALL RETI The status bit is affected −...
Page 56: Jumps
Instruction Set 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format Op-code Table 3−13 lists and describes the jump instructions. Table 3−13.Jump Instructions Mnemonic JEQ/JZ JNE/JNZ Conditional jumps support program branching relative to the PC and do not affect the status bits.
Page 57 ADC[.W] Add carry to destination ADC.B Add carry to destination Syntax ADC.B Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise...
Page 58 Instruction Set ADD[.W] Add source to destination ADD.B Add source to destination Syntax src,dst ADD.B src,dst Operation src + dst −> dst Description The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise...
Page 59 ADDC[.W] Add source and carry to destination ADDC.B Add source and carry to destination Syntax ADDC ADDC.B Operation src + dst + C −> dst Description The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected.
Page 60 Instruction Set AND[.W] Source AND destination AND.B Source AND destination Syntax AND.B Operation src .AND. dst −> dst Description The source operand and the destination operand are logically ANDed. The result is placed into the destination. Status Bits N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
Page 61 BIC[.W] Clear bits in destination BIC.B Clear bits in destination Syntax BIC.B Operation .NOT.src .AND. dst −> dst Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.
Page 62 Instruction Set BIS[.W] Set bits in destination BIS.B Set bits in destination Syntax BIS.B Operation src .OR. dst −> dst Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected.
Page 63 BIT[.W] Test bits in destination BIT.B Test bits in destination Syntax Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. Status Bits N: Set if MSB of result is set, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT.
Page 64 Instruction Set * BR, BRANCH Branch to ... destination Syntax Operation dst −> PC Emulation dst,PC Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction.
Page 65 CALL Subroutine Syntax CALL Operation SP − 2 Description A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction.
Page 66 Instruction Set * CLR[.W] Clear destination * CLR.B Clear destination Syntax CLR.B Operation 0 −> dst Emulation MOV.B Description The destination operand is cleared. Status Bits Status bits are not affected. Example RAM word TONI is cleared. Example Register R5 is cleared. Example RAM byte TONI is cleared.
Page 67 * CLRC Clear carry bit Syntax CLRC Operation 0 −> C Emulation #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not affected Z: Not affected C: Cleared V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 68 Instruction Set * CLRN Clear negative bit Syntax CLRN 0 → N Operation (.NOT.src .AND. dst −> dst) Emulation #4,SR Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction.
Page 69 * CLRZ Clear zero bit Syntax CLRZ 0 → Z Operation (.NOT.src .AND. dst −> dst) Emulation #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction.
Page 70 Instruction Set CMP[.W] Compare source and destination CMP.B Compare source and destination Syntax CMP.B Operation dst + .NOT.src + 1 (dst − src) Description The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored;...
Page 71 * DADC[.W] Add carry decimally to destination * DADC.B Add carry decimally to destination Syntax DADC DADC.B Operation dst + C −> dst (decimally) Emulation DADD DADD.B Description The carry bit (C) is added decimally to the destination. Status Bits N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise...
Page 72 Instruction Set DADD[.W] Source and carry added decimally to destination DADD.B Source and carry added decimally to destination Syntax DADD DADD.B Operation src + dst + C −> dst (decimally) Description The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs.
Page 73 * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC.B Operation dst − 1 −> dst Emulation #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 74 Instruction Set * DECD[.W] Double-decrement destination * DECD.B Double-decrement destination Syntax DECD DECD.B Operation dst − 2 −> dst Emulation #2,dst Emulation SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 75 * DINT Disable (general) interrupts Syntax DINT 0 → GIE Operation (0FFF7h .AND. SR → SR Emulation #8,SR Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status Bits Status bits are not affected.
Page 76 Instruction Set * EINT Enable (general) interrupts Syntax EINT 1 → GIE Operation (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR.
Page 77 * INC[.W Increment destination * INC.B Increment destination Syntax INC.B Operation dst + 1 −> dst Emulation #1,dst Description The destination operand is incremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise...
Page 78 Instruction Set * INCD[.W] Double-increment destination * INCD.B Double-increment destination Syntax INCD INCD.B Operation dst + 2 −> dst Emulation #2,dst Emulation ADD.B #2,dst Example The destination operand is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise...
Page 79 * INV[.W] Invert destination * INV.B Invert destination Syntax INV.B Operation .NOT.dst −> dst Emulation #0FFFFh,dst Emulation XOR.B #0FFh,dst Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
Page 80 Instruction Set Jump if carry set Jump if higher or same Syntax label label If C = 1: PC + 2 × offset −> PC Operation If C = 0: execute following instruction Description The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 81 JEQ, JZ Jump if equal, jump if zero Syntax label, If Z = 1: PC + 2 × offset −> PC Operation If Z = 0: execute following instruction Description The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 82 Instruction Set Jump if greater or equal Syntax label If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −> PC Operation If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 83 Jump if less Syntax label If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PC Operation If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 84 Instruction Set Jump unconditionally Syntax label PC + 2 × offset −> PC Operation Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status Bits Status bits are not affected. Hint: This one-word instruction replaces the BRANCH instruction in the range of −511 to +512 words relative to the current program counter.
Page 85 Jump if negative Syntax label if N = 1: PC + 2 × offset −> PC Operation if N = 0: execute following instruction Description The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 86 Instruction Set Jump if carry not set Jump if lower Syntax label label if C = 0: PC + 2 × offset −> PC Operation if C = 1: execute following instruction Description The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 87 Jump if not equal Jump if not zero Syntax label label If Z = 0: PC + 2 × offset −> PC Operation If Z = 1: execute following instruction Description The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 88 Instruction Set MOV[.W] Move source to destination MOV.B Move source to destination Syntax MOV.B Operation src −> dst Description The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status Bits Status bits are not affected.
Page 89 * NOP No operation Syntax Operation None Emulation #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. The NOP instruction is mainly used for two purposes: To fill one, two, or three memory words To adjust software timing...
Page 90 Instruction Set * POP[.W] Pop word from stack to destination * POP.B Pop byte from stack to destination Syntax POP.B Operation @SP −> temp SP + 2 −> SP temp −> dst Emulation Emulation MOV.B Description The stack location pointed to by the stack pointer (TOS) is moved to the destination.
Page 91 PUSH[.W] Push word onto stack PUSH.B Push byte onto stack Syntax PUSH PUSH.B SP − 2 → SP Operation src → @SP Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status Bits Status bits are not affected.
Page 92 Instruction Set * RET Return from subroutine Syntax Operation @SP→ PC SP + 2 → SP Emulation @SP+,PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call.
Page 93 RETI Return from interrupt Syntax RETI Operation SP + 2 SP + 2 Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two.
Page 94 Instruction Set * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA.B Operation C <− MSB <− MSB−1 ... LSB+1 <− LSB <− 0 Emulation dst,dst ADD.B dst,dst Description The destination operand is shifted left one position as shown in Figure 3−14. The MSB is shifted into the carry bit (C) and the LSB is filled with 0.
Page 95 * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC.B Operation C <− MSB <− MSB−1 ... LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 3−15. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Page 96 Instruction Set RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA.B Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, Description The destination operand is shifted right one position as shown in Figure 3−16. The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the LSB+1 is shifted into the LSB.
Page 97 RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax Operation C −> MSB −> MSB−1 ... LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C). Figure 3−17.
Page 98 Instruction Set * SBC[.W] Subtract source and borrow/.NOT. carry from destination * SBC.B Subtract source and borrow/.NOT. carry from destination Syntax SBC.B Operation dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst Emulation SUBC #0,dst SUBC.B #0,dst Description...
Page 99 * SETC Set carry bit Syntax SETC Operation 1 −> C Emulation #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example Emulation of the decimal subtraction: Subtract R5 from R6 decimally...
Page 100 Instruction Set * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. RISC 16−Bit CPU 3-64...
Page 101 * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation #2,SR Description The zero bit (Z) is set. Status Bits N: Not affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Instruction Set RISC 16−Bit CPU 3-65...
Page 102 Instruction Set SUB[.W] Subtract source from destination SUB.B Subtract source from destination Syntax src,dst SUB.B src,dst Operation dst + .NOT.src + 1 −> dst [(dst − src −> dst)] Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the constant 1.
Page 103 SUBC[.W]SBB[.W] Subtract source and borrow/.NOT. carry from destination SUBC.B,SBB.B Subtract source and borrow/.NOT. carry from destination Syntax SUBC src,dst src,dst SUBC.B src,dst Operation dst + .NOT.src + C −> dst (dst − src − 1 + C −> dst) Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C).
Page 104 Instruction Set SWPB Swap bytes Syntax SWPB Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 105 Extend Sign Syntax Operation Bit 7 −> Bit 8 ... Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3−19. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT.
Page 106 Instruction Set * TST[.W] Test destination * TST.B Test destination Syntax TST.B Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMP.B Description The destination operand is compared with zero. The status bits are set accord- ing to the result. The destination is not affected. Status Bits N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise...
Page 107 XOR[.W] Exclusive OR of source with destination XOR.B Exclusive OR of source with destination Syntax XOR.B Operation src .XOR. dst −> dst Description The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. Status Bits N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise...
Page 108: Instruction Cycles And Lengths
Instruction Set 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles Table 3−14 lists the CPU cycles for interrupt overhead and reset.
Page 109 Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3−16.Format 1 Instruction Cycles and Lengths Addressing Mode @Rn+ @Rn+ x(Rn) x(Rn) &EDE &EDE No. of No. of Length of Length of Cycles...
Page 110: Instruction Set Description
Instruction Set 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction set is summarized in Table 3−17. Figure 3−20. Core Instruction Map 0xxx 4xxx 8xxx Cxxx 1xxx RRC.B SWPB RRA.B 14xx 18xx 1Cxx 20xx 24xx 28xx...
Page 111 Table 3−17.MSP430 Instruction Set Mnemonic Description ADC(.B) † Add C to destination Add source to destination ADD(.B) src,dst Add source and C to destination ADDC(.B) src,dst AND source and destination AND(.B) src,dst Clear bits in destination BIC(.B) src,dst Set bits in destination BIS(.B) src,dst Test bits in destination...
Page 112 3-76...
Page 113 Basic Clock Module The basic clock module provides the clocks for MSP430x1xx devices. This chapter describes the operation of the basic clock module. The basic clock module is implemented in all MSP430x1xx devices. Topic Basic Clock Module Introduction Basic Clock Module Operation...
Page 114: Basic Clock Module Introduction
Basic Clock Module Introduction 4.1 Basic Clock Module Introduction The basic clock module supports low system cost and ultralow-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The basic clock module can be configured to operate without any external components, with one external resistor, with one or two external crystals, or with resonators, under full software control.
Page 115 Figure 4−1. Basic Clock Block Diagram OSCOFF XTS 12pF LFOff 12pF XOUT LFXT1 Oscillator XT2OFF XT2IN XT2OUT XT2 Oscillator DCOR SCG0 RSELx DCOx Generator P2.5/Rosc Note: XT2 Oscillator The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx devices. The LFXT1CLK is used in place of XT2CLK. Basic Clock Module Introduction LFXT1CLK XT1Off...
Page 116: Basic Clock Module Operation
BIS.B #RSEL2+RSEL1+RSEL0,&BCSCTL1 ; BIS.B #DCO2+DCO1+DCO0,&DCOCTL 4.2.1 Basic Clock Module Features for Low-Power Applications Conflicting requirements typically exist in battery-powered MSP430x1xx applications: Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing...
Page 117 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS = 0). A watch crystal connects to XIN and XOUT without any other external components. Internal 12-pF load capacitors are provided for LFXT1 in LF mode. The capacitors add serially, providing a match for standard 32,768-Hz crystals requiring a 6-pF load.
Page 118: Xt2 Oscillator
Basic Clock Module Operation 4.2.3 XT2 Oscillator Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode. The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as shown in Figure 4−3.
Page 119 Adjusting the DCO frequency After a PUC, the internal resistor is selected for the DC generator, RSELx = 4, and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLK and SMCLK are sourced from DCOCLK. Because the CPU executes code from MCLK, which is sourced from the fast-starting DCO, code execution begins from PUC in less than 6 µs.
Page 120 Basic Clock Module Operation Using an External Resistor (R The DCO temperature coefficient can be reduced by using an external resistor tied to DV shows the typical relationship of f external resistor options. Using an external R temperature coefficient to approximately 0.1%/C. See the device-specific data sheet for parameters.
Page 121: Dco Modulator
4.2.5 DCO Modulator The modulator mixes two DCO frequencies, f intermediate effective frequency between f clock energy, reducing electromagnetic interference (EMI) mixes f and f MODx bits. When MODx = 0 the modulator is off. The modulator mixing formula is: t =(32−...
Page 122: Basic Clock Module Fail-Safe Operation
Basic Clock Module Operation 4.2.6 Basic Clock Module Fail-Safe Operation The basic clock module incorporates an oscillator-fault detection fail-safe feature. The oscillator fault detector is an analog circuit that monitors the LFXT1CLK (in HF mode) and the XT2CLK. An oscillator fault is detected when either clock signal is not present for approximately 50 µs.
Page 123 Oscillator Fault Detection Signal XT_OscFault triggers the OFIFG flag as shown in Figure 4−10. The LFXT1_OscFault signal is low when LFXT1 is in LF mode. On devices without XT2, the OFIFG flag cannot be cleared when LFXT1 is in LF mode. MCLK may be sourced by LFXT1CLK in LF mode by setting the SELMx bits, even though OFIFG remains set.
Page 124 Basic Clock Module Operation Sourcing MCLK from a Crystal After a PUC, the basic clock module uses DCOCLK for MCLK. If required, MCLK may be sourced from LFXT1 or XT2. The sequence to switch the MCLK source from the DCO clock to the crystal clock (LFXT1CLK or XT2CLK) is: 1) Switch on the crystal oscillator 2) Clear the OFIFG flag...
Page 125: Synchronization Of Clock Signals
4.2.7 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to the another, the switch is synchronized to avoid critical race conditions as shown in Figure 4−11: 1) The current clock cycle continues until the next rising edge. 2) The clock remains high until the next rising edge of the new clock.
Page 126: Basic Clock Module Registers
Basic Clock Module Registers 4.3 Basic Clock Module Registers The basic clock module registers are listed in Table 4−1: Table 4−1. Basic Clock Module Registers Register DCO control register Basic clock system control 1 Basic clock system control 2 SFR interrupt enable register 1 SFR interrupt flag register 1 4-14 Basic Clock Module...
Page 127 DCOCTL, DCO Control Register DCOx rw−0 rw−1 rw−1 DCOx Bits DCO frequency select. These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected. MODx Bits Modulator selection. These bits define how often the f used within a period of 32 DCOCLK cycles.
Page 128 Basic Clock Module Registers BCSCTL2, Basic Clock System Control Register 2 SELMx DIVMx rw−(0) rw−(0) rw−(0) SELMx Bits Select MCLK. These bits select the MCLK source. DCOCLK DCOCLK XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2 oscillator not present on-chip. LFXT1CLK DIVMx BitS...
Page 129 IE1, Interrupt Enable Register 1 Bits These bits may be used by other modules. See device-specific datasheet. OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 130 4-18 Basic Clock Module...
Page 131: Flash Memory Controller
Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller. Topic Flash Memory Introduction ........Flash Memory Segmentation .
Page 132: Flash Memory Introduction
Flash Memory Introduction 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has three registers, a timing generator, and a voltage generator to supply program and erase voltages.
Page 133: Flash Memory Segmentation
5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory sections.
Page 134: Flash Memory Timing Generator
Flash Memory Operation 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage.
Page 135: Erasing Flash Memory
5.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. There are three erase modes selected with the ERASE and MERAS bits listed in Table 5−1.
Page 136 Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes.
Page 137 Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again.
Page 138: Writing Flash Memory
Flash Memory Operation 5.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 5−1. Table 5−2. Write Modes BLKWRT Both write modes use a sequence of individual write instructions, but using the block write mode is approximately twice as fast as byte/word mode, because the voltage generator remains on for the complete block write.
Page 139 In byte/word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for 32 of the 35 f cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates.
Page 140 Flash Memory Operation Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5−9. Figure 5−9. Initiating a Byte/Word Write from RAM Disable all interrupts and watchdog Setup flash controller and set WRT=1 Write byte or word Set WRT=0, LOCK = 1 re-enable interrupts and watchdog...
Page 141: Block Write
Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time t a block write.
Page 142 Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 5−8 and the following example. Figure 5−11. Block Write Flow Disable all interrupts and watchdog Setup flash controller Set BLKWRT=WRT=1 Write byte or word Set BLKWRT=0 Set WRT=0, LOCK=1 re-enable interrupts and WDT...
Page 143 ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. #32,R5 #0F000h,R6 #WDTPW+WDTHOLD,&WDTCTL DINT L1 BIT #BUSY,&FCTL3 #FWKEY+FSSEL1+FN0,&FCTL2 ;...
Page 144: Flash Memory Access During Write Or Erase
Flash Memory Operation 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable.
Page 145: Configuring And Accessing The Flash Memory Controller
5.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset.
Page 146 Flash Memory Operation Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interface requires four signals (5 signals on 20- and 28-pin devices), ground and optionally V The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible.
Page 147: Flash Memory Registers
5.4 Flash Memory Registers The flash memory registers are listed in Table 5−4. Table 5−4. Flash Memory Registers Register Flash memory control register 1 Flash memory control register 2 Flash memory control register 3 Interrupt Enable 1 Short Form Register Type Address FCTL1 Read/write 0128h...
Page 148 Flash Memory Registers FCTL1, Flash Memory Control Register FWKEY, Must be written as 0A5h BLKWRT Reserved rw−0 rw−0 FRKEY/ Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC FWKEY 15-8 will be generated. BLKWRT Bit 7 Block write mode.
Page 149 FCTL2, Flash Memory Control Register FSSELx rw−0 rw−1 rw-0 FWKEYx Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC 15-8 will be generated. FSSELx Bits Flash controller clock source select 7−6 ACLK MCLK SMCLK SMCLK Bits Flash controller clock divider.
Page 150 Flash Memory Registers FCTL3, Flash Memory Control Register FCTL3 Reserved Reserved EMEX rw-0 FWKEYx Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC 15-8 will be generated. Reserved Bits Reserved. Always read as 0. EMEX Bit 5 Emergency exit...
Page 151 IE1, Interrupt Enable Register 1 ACCVIE rw−0 Bits These bits may be used by other modules. See device-specific datasheet. 7-6, ACCVIE Bit 5 Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 152 5-22 Flash Memory Controller...
Page 153: Supply Voltage Supervisor
Supply Voltage Supervisor This chapter describes the operation of the SVS. The SVS is implemented in MSP430x15x and MSP430x16x devices. Topic SVS Introduction ..........SVS Operation .
Page 154: Svs Introduction
SVS Introduction 6.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the AV voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold.
Page 155 Figure 6−1. SVS Block Diagram AV CC AV CC SVSIN 1111 1101 − 1100 0011 0010 1.25V 0001 Brownout Reset ~ 50us t Reset ~ 50us Set SVSFG PORON SVSON SVSOP SVSFG Supply Voltage Supervisor SVS Introduction SVS_POR SVSOUT Reset SVSCTL Bits...
Page 156: Svs Comparator Operation
SVS Operation 6.2 SVS Operation The SVS detects if the AV configured to provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 6.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V VLDx = 0 and on when VLDx >...
Page 157: Changing The Vldx Bits
6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented to allows the SVS circuitry to settle. During each delay, the SVS will not set SVSFG. The delays, t delay takes affect when VLDx is changed from zero to any non-zero d(SVSon) value and is a approximately 50 µs.
Page 158: Svs Operating Range
SVS Operation 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AV SVS/Brownout interoperation are shown in Figure 6−3. Figure 6−3. Operating Levels for SVS and Brownout/Reset Circuit V hys(SVS_IT−) V (SVS_IT−) V (SVSstart) V hys(B_IT−) V (B_IT−)
Page 159: Svs Registers
6.3 SVS Registers The SVS registers are listed in Table 6−1. Table 6−1. SVS Registers Register SVS Control Register SVSCTL, SVS Control Register VLDx rw−0 † rw−0 † rw−0 † † Reset by a brownout reset only, not by a POR or PUC. VLDx Bits Voltage level detect.
Page 160 Supply Voltage Supervisor...
Page 161: Hardware Multiplier
Hardware Multiplier This chapter describes the hardware multiplier. The hardware multiplier is implemented in MSP430x14x and MSP430x16x devices. Topic Hardware Multiplier Introduction Hardware Multiplier Operation Hardware Multiplier Registers ........Chapter 7 Page .
Page 162: Hardware Multiplier Introduction
Hardware Multiplier Introduction 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Page 163: Hardware Multiplier Operation
7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT.
Page 164: Result Registers
Hardware Multiplier Operation 7.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in Table 7−2. Table 7−2. RESHI Contents Mode MPYS MACS...
Page 165: Software Examples
7.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. ; 16x16 Unsigned Multiply ;...
Page 166: Indirect Addressing Of Reslo
Hardware Multiplier Operation 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one instruction is needed between loading the second operand and accessing one of the result registers: ; Access multiplier results with indirect addressing 7.2.5 Using Interrupts If an interrupt occurs after writing OP1, but before writing OP2, and the...
Page 167: Hardware Multiplier Registers
7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7−4. Table 7−4. Hardware Multiplier Registers Register Operand one - multiply Operand one - signed multiply Operand one - multiply accumulate Operand one - signed multiply accumulate MACS Operand two Result low word Result high word...
Page 168 Hardware Multiplier...
Page 169: Dma Controller
The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. The DMA controller is implemented in MSP430x15x and MSP430x16x devices. Topic DMA Introduction ..........DMA Operation .
Page 170: Dma Introduction
8.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power mode without having to awaken to move data to or from a peripheral.
Page 171 Figure 8−1. DMA Controller Block Diagram DMA0TSELx Halt DMAREQ 0000 TACCR2_CCIFG 0001 TBCCR2_CCIFG 0010 USART0 data received 0011 USART0 transmit ready 0100 DAC12_0IFG 0101 ADC12IFGx 0110 TACCR0_CCIFG 0111 TBCCR0_CCIFG 1000 USART1 data received 1001 USART1 transmit ready 1010 Multiplier ready 1011 No trigger −−−...
Page 172: Dma Addressing Modes
8.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses.
Page 173: Dma Transfer Modes
8.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 8−1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode.
Page 174 Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 8−3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer.
Page 175 Figure 8−3. DMA Single Transfer State Diagram DMAEN = 0 DMAEN = 0 DMAEN = 1 DMAREQ = 0 T_Size → DMAxSZ DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd [ DMADTx = 0 AND DMAxSZ = 0] OR DMAEN = 0 DMAABORT = 1 DMAABORT=0 Wait for Trigger...
Page 176 Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered.
Page 177 Figure 8−4. DMA Block Transfer State Diagram DMAEN = 0 DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size → DMAxSZ DMAxSZ → T_Size [DMADTx = 1 DMAxSA → T_SourceAdd AND DMAxSZ = 0] DMAxDA → T_DestAdd DMAEN = 0 DMAABORT = 1 DMAABORT=0 Wait for Trigger...
Page 178 Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared.
Page 179 Figure 8−5. DMA Burst-Block Transfer State Diagram DMAEN = 0 DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size → DMAxSZ DMAxSZ → T_Size [DMADTx = {2, 3} DMAxSA → T_SourceAdd DMAxDA → T_DestAdd AND DMAxSZ = 0] DMAEN = 0 DMAABORT = 1 DMAABORT=0 Wait for Trigger...
Page 180: Initiating Dma Transfers
8.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 8−2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place.
Page 181 Table 8−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset when the transfer starts.
Page 182: Stopping Dma Transfers
8.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. A burst-block transfer may be stopped by clearing the DMAEN bit. 8.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0−DMA1−DMA2.
Page 183: Dma Transfer Cycle Time
8.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the DMA cycle time is dependent on the MSP430 operating mode and clock system setup.
Page 184: Using Dma With System Interrupts
8.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine.
Page 185: Using Adc12 With The Dma Controller
8.2.9 Using the I C Module with the DMA Controller The I C module provides two trigger sources for the DMA controller. The I module can trigger a transfer when new I transmit data is needed. The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the I be used to transfer data from the I data.
Page 186: Dma Registers
8.3 DMA Registers The DMA registers are listed in Table 8−4: Table 8−4. DMA Registers Register DMA control 0 DMA control 1 DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address...
Page 187 DMACTL0, DMA Control Register 0 Reserved rw−(0) rw−(0) rw−(0) DMA1TSELx rw−(0) rw−(0) rw−(0) Reserved Bits Reserved 15−12 DMA2 Bits DMA trigger select. These bits select the DMA transfer trigger. TSELx 11−8 0000 DMAREQ bit (software trigger) 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFG0 (UART/SPI mode), USART0 data received (I 0100 UTXIFG0 (UART/SPI mode), USART0 transmit ready (I...
Page 188 DMACTL1, DMA Control Register 1 Reserved Bits Reserved. Read only. Always read as 0. 15−3 Bit 2 DMA on fetch ONFETCH The DMA transfer occurs immediately The DMA transfer occurs on next instruction fetch after the trigger ROUND Bit 1 Round robin.
Page 189 DMAxCTL, DMA Channel x Control Register Reserved DMADTx rw−(0) rw−(0) rw−(0) DMALEVEL DSTBYTE SRCBYTE rw−(0) rw−(0) rw−(0) Reserved Bit 15 Reserved DMADTx Bits DMA Transfer mode. 14−12 000 Single transfer 001 Block transfer 010 Burst-block transfer 011 Burst-block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst-block transfer 111 Repeated burst-block transfer...
Page 190 Bit 6 DMA source byte. This bit selects the source as a byte or word. SRCBYTE Word Byte Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive LEVEL triggers. Edge sensitive (rising edge) Level sensitive (high level) DMAEN Bit 4 DMA enable Disabled...
Page 191 DMAxDA, DMA Destination Address Register DMAxDAx Bits DMA destination address. The destination address register points to the 15−0 destination address for single transfers or the first address for block transfers. The DMAxDA register remains unchanged during block and burst-block transfers. DMAxSZ, DMA Size Address Register DMAxSZx Bits...
Page 192 8-24...
Page 193: Digital I/O
This chapter describes the operation of the digital I/O ports. Ports P1-P2 are implemented in MSP430x11xx devices. Ports P1-P3 are implemented in MSP430x12xx devices. Ports P1-P6 are implemented in MSP430x13x, MSP430x14x, MSP430x15x, and MSP430x16x devices. Topic Digital I/O Introduction ........Digital I/O Operation .
Page 194: Digital I/O Introduction
Digital I/O Introduction 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to. Ports P1 and P2 have interrupt capability.
Page 195: Digital I/O Operation
9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections. 9.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function.
Page 196: Function Select Registers Pxsel
Digital I/O Operation 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function − I/O port or peripheral module function. Bit = 0: I/O Function is selected for the pin Bit = 1: Peripheral module function is selected for the pin Setting PxSELx = 1 does not automatically set the pin direction.
Page 197: P1 And P2 Interrupts
9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt.
Page 198: Configuring Unused Port Pins
Digital I/O Operation Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxIESx Writing to P1IES, or P2IES can result in setting the corresponding interrupt flags.
Page 199: Digital I/O Registers
9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used to configure ports P3 - P6. The digital I/O registers are listed in Table 9−1. Table 9−1. Digital I/O Registers Port Register Short Form P1IN Input P1OUT...
Page 200 Digital I/O...
Page 201: Watchdog Timer
The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the watchdog timer. The watchdog timer is implemented in all MSP430x1xx devices. Topic 10.1 Watchdog Timer Introduction ....... . .
Page 202: Watchdog Timer Introduction
Watchdog Timer Introduction 10.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
Page 203 Figure 10−1. Watchdog Timer Block Diagram WDTQn Int. Flag Pulse Generator SMCLK ACLK 16−bit Password Counter Compare Clear (Asyn) WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0 Watchdog Timer Introduction WDTCTL 16−bit Write Enable Low Byte R / W Watchdog Timer 10-3...
Page 204: Watchdog Timer Operation
Watchdog Timer Operation 10.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected, read/write register.
Page 205: Watchdog Timer Interrupts
10.2.4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. The WDT interrupt flag, WDTIFG, located in IFG1.0 The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the WDTIFG flag sources a reset vector interrupt.
Page 206: Software Examples
Watchdog Timer Operation 10.2.5 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user’s application and the type of clocking used determine how the WDT should be configured.
Page 207: Watchdog Timer Registers
10.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10−1. Table 10−1.Watchdog Timer Registers Register Watchdog timer control register SFR interrupt enable register 1 SFR interrupt flag register 1 † WDTIFG is reset with POR Short Form Register Type Address WDTCTL Read/write...
Page 208 Watchdog Timer Registers WDTCTL, Watchdog Timer Register WDTPW, must be written as 05Ah WDTHOLD WDTNMIES WDTNMI rw−0 rw−0 rw−0 WDTPW Bits Watchdog timer password. Always read as 069h. Must be written as 05Ah, or 15-8 a PUC will be generated. WDTHOLD Bit 7 Watchdog timer hold.
Page 209 IE1, Interrupt Enable Register 1 Bits These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 210 Watchdog Timer Registers IFG1, Interrupt Flag Register 1 Bits These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 211: Timer_A
Timer_A is a 16-bit timer/counter with three capture/compare registers. This chapter describes Timer_A. Timer_A is implemented in all MSP430x1xx devices. Topic 11.1 Timer_A Introduction .........
Page 212: Timer_A Introduction
Timer_A Introduction 11.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Page 213 Figure 11−1. Timer_A Block Diagram Timer Clock TASSELx TACLK Divider 1/2/4/8 ACLK SMCLK INCLK CCISx CCI2A Capture Mode CCI2B Timer Clock SCCI Output Unit2 EQU0 OUTMODx 16−bit Timer Clear TACLR logic TACCR2 Sync Compararator 2 EQU2 D Set Q Timer Clock Reset Timer_A Introduction Timer Block...
Page 214: Timer_A Operation
Timer_A Operation 11.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in the following sections. 11.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TAR can be read or written with software.
Page 215: Starting The Timer
11.2.2 Starting the Timer The timer may be started, or restarted in the following ways: The timer counts when MCx > 0 and the clock source is active. When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0.
Page 216 Timer_A Operation Up Mode The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 11−2. The number of timer counts in the period is TACCR0+1.
Page 217: Continuous Mode
Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 11−4. The capture/compare register TACCR0 works the same way as the other capture/compare registers. Figure 11−4. Continuous Mode 0FFFFh The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero.
Page 218 Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx register in the interrupt service routine.
Page 219 Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero, as shown in Figure 11−7.
Page 220 Timer_A Operation Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The new period takes affect after the counter counts down to zero. When the timer is counting in the up direction, and the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period before counting down.
Page 221: Capture/Compare Blocks
The timer value is copied into the TACCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB.
Page 222: Compare Mode
Timer_A Operation Figure 11−11. Capture Cycle Capture Taken Clear Bit COV in Register TACCTLx Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between V changes state: Compare Mode...
Page 223: Output Unit
11.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output modes are defined by the OUTMODx bits and are described in Table 11−2.
Page 224 Timer_A Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 11−12 using TACCR0 and TACCR1. Figure 11−12.Output Example—Timer in Up Mode 0FFFFh TACCR0...
Page 225 Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 11−13 using TACCR0 and TACCR1. Figure 11−13.Output Example—Timer in Continuous Mode 0FFFFh TACCR0 TACCR1...
Page 226 Timer_A Operation Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 11−14 using TACCR0 and TACCR2. Figure 11−14.Output Example—Timer in Up/Down Mode 0FFFFh TACCR0...
Page 227: Timer_A Interrupts
11.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: TACCR0 interrupt vector for TACCR0 CCIFG TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register.
Page 228 Timer_A Operation TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 229: Timer_A Registers
11.3 Timer_A Registers The Timer_A registers are listed in Table 11−3: Table 11−3. Timer_A Registers Register Timer_A control Timer_A counter Timer_A capture/compare control 0 Timer_A capture/compare 0 Timer_A capture/compare control 1 Timer_A capture/compare 1 Timer_A capture/compare control 2 Timer_A capture/compare 2 Timer_A interrupt vector Short Form Register Type Address...
Page 230 Timer_A Registers TACTL, Timer_A Control Register Unused rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bits Unused 15-10 TASSELx Bits Timer_A clock source select TACLK ACLK SMCLK INCLK Bits Input divider. These bits select the divider for the input clock. Bits Mode control.
Page 231 TAR, Timer_A Register rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Bits Timer_A register. The TAR register is the count of Timer_A. TARx 15-0 TARx rw−(0) rw−(0) rw−(0) TARx rw−(0) rw−(0) rw−(0) Timer_A Registers rw−(0) rw−(0) rw−(0) rw−(0) Timer_A 11-21...
Page 232 Timer_A Registers TACCTLx, Capture/Compare Control Register CCISx rw−(0) rw−(0) rw−(0) OUTMODx rw−(0) rw−(0) rw−(0) Capture mode 15-14 No capture Capture on rising edge Capture on falling edge Capture on both rising and falling edges CCISx Capture/compare input select. These bits select the TACCRx input signal. 13-12 See the device-specific datasheet for specific signal connections.
Page 233 CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. Interrupt disabled Interrupt enabled Bit 3 Capture/compare input. The selected input signal can be read by this bit. Bit 2 Output. For output mode 0, this bit directly controls the state of the output. Output low Output high Bit 1...
Page 234 11-24 Timer_A...
Page 235: Timer_B
Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_B. Timer_B3 (three capture/compare registers) is implemented in MSP430x13x and MSP430x15x devices. Timer_B7 (seven capture/compare registers) implemented MSP430x16x devices. Topic 12.1 Timer_B Introduction ......... 12.2 Timer_B Operation .
Page 236: Similarities And Differences From Timer_A
Timer_B Introduction 12.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Page 237 Figure 12−1. Timer_B Block Diagram Timer Clock TBSSELx TBCLK Divider 1/2/4/8 ACLK SMCLK TBCLGRPx Group Load Logic CCISx CCI6A Capture Mode CCI6B Timer Clock CLLDx TBR=0 CCR5 EQU0 CCR4 UP/DOWN CCR1 Output Unit6 EQU0 OUTMODx 16−bit Timer Clear 10 12 16 TBCLR logic TBCCR6...
Page 238: Timer_B Operation
Timer_B Operation 12.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 12.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software.
Page 239: Timer Mode Control
12.2.2 Starting the Timer The timer may be started or restarted in the following ways: The timer counts when MCx > 0 and the clock source is active. When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0.
Page 240 Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 12−2. The number of timer counts in the period is TBCL0+1.
Page 241 Continuous Mode In continuous mode the timer repeatedly counts up to TBR from zero as shown in Figure 12−4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 12−4. Continuous Mode TBR (max) The TBIFG interrupt flag is set when the timer counts from TBR Figure 12−5 shows the flag set cycle.
Page 242 Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine.
Page 243 Up/Down Mode The up/down mode is used if the timer period must be different from TBR counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 12−7.
Page 244 Timer_B Operation Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the down direction, and when the TBCL0 load mode is immediate, the timer continues its descent until it reaches zero. The new period takes effect after the counter counts down to zero.
Page 245: Capture/Compare Blocks
The timer value is copied into the TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB.
Page 246 Timer_B Operation Figure 12−11.Capture Cycle Capture Taken Clear Bit COV in Register TBCCTLx Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets bit CCIS1=1 and toggles bit CCIS0 to switch the capture signal between V CCIS0 changes state: Compare Mode...
Page 247 Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates. The user cannot directly access TBCLx.
Page 248: Output Unit
Timer_B Operation 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a high-impedance state.
Page 249 Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 12−12 using TBCL0 and TBCL1. Figure 12−12.
Page 250 Timer_B Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 12−13 using TBCL0 and TBCL1. Figure 12−13. Output Example—Timer in Continuous Mode TBR (max) TBCL0 TBCL1...
Page 251 Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 12−14 using TBCL0 and TBCL3. Figure 12−14.
Page 252: Timer_B Interrupts
Timer_B Operation 12.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: TBCCR0 interrupt vector for TBCCR0 CCIFG TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register.
Page 253 TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction.
Page 254: Timer_B Registers
Timer_B Registers 12.3 Timer_B Registers The Timer_B registers are listed in Table 12−5: Table 12−5.Timer_B Registers Register Timer_B control Timer_B counter Timer_B capture/compare control 0 Timer_B capture/compare 0 Timer_B capture/compare control 1 Timer_B capture/compare 1 Timer_B capture/compare control 2 Timer_B capture/compare 2 Timer_B capture/compare control 3 Timer_B capture/compare 3 Timer_B capture/compare control 4...
Page 255 Timer_B Control Register TBCTL Unused TBCLGRPx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bit 15 Unused TBCLGRP TBCLx group 14-13 Each TBCLx latch loads independently TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)
Page 256 Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request. Interrupt disabled Interrupt enabled TBIFG...
Page 257 TBCCTLx, Capture/Compare Control Register CCISx rw−(0) rw−(0) rw−(0) OUTMODx rw−(0) rw−(0) rw−(0) Capture mode 15-14 No capture Capture on rising edge Capture on falling edge Capture on both rising and falling edges CCISx Capture/compare input select. These bits select the TBCCRx input signal. 13-12 See the device-specific datasheet for specific signal connections.
Page 258 Timer_B Registers CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. Interrupt disabled Interrupt enabled Bit 3 Capture/compare input. The selected input signal can be read by this bit. Bit 2 Output. For output mode 0, this bit directly controls the state of the output. Output low Output high Bit 1...
Page 259 TBIV, Timer_B Interrupt Vector Register Bits Timer_B interrupt vector value TBIVx 15-0 TBIV Contents † MSP430x14x, MSP430x16x devices only TBIVx r−(0) r−(0) r−(0) Interrupt Source Interrupt Flag No interrupt pending − Capture/compare 1 TBCCR1 CCIFG Capture/compare 2 TBCCR2 CCIFG † Capture/compare 3 TBCCR3 CCIFG †...
Page 260 12-26 Timer_B...
Page 261: Usart Peripheral Interface, Uart Mode
USART Peripheral Interface, UART Mode universal synchronous/asynchronous peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430x12xx, MSP430x13xx, and MSP430x15x devices. In addition to USART0, the MSP430x14x and MSP430x16x devices implement a second identical USART module, USART1.
Page 262: Usart Introduction: Uart Mode
USART Introduction: UART Mode 13.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared. UART mode features include: 7- or 8-bit data with odd, even, or non-parity Independent transmit and receive shift registers Separate transmit and receive buffer registers...
Page 263 Figure 13−1. USART Block Diagram: UART Mode SWRST URXEx* URXEIE URXWIE Receive Control Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 CHAR Baud−Rate Generator UCLKI ACLK Prescaler/Divider UxBRx SMCLK SMCLK Modulator UxMCTL CHAR Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF UTXIFGx*...
Page 264: Usart Initialization And Reset
USART Operation: UART Mode 13.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency.
Page 265: Asynchronous Communication Formats
13.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When MM = 0, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 13−3.
Page 266 USART Operation: UART Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF, and interrupts are not generated. When an address character is received, the receiver is temporarily activated to transfer the character to UxRXBUF and sets the URXIFGx interrupt flag.
Page 267 Address Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 13−4. The first character in a block of characters carries a set address bit which indicates that the character is an address.
Page 268 USART Operation: UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t will be ignored. See the device-specific datasheet for parameters. When a low period on URXDx exceeds t bit.
Page 269: Usart Receive Enable
13.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 13−5. Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active. The receive-data buffer, UxRXBUF, contains the character moved from the RX shift register after the character is received.
Page 270: Usart Transmit Enable
USART Operation: UART Mode 13.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty, and transmission begins.
Page 271: Uart Baud Rate Generation
13.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 13−7. This combination supports fractional divisors for baud rate generation. The maximum USART baud rate is one-third the UART source clock frequency BRCLK.
Page 272 USART Operation: UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit period of N BRCLKs.
Page 273 Transmit Bit Timing The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced. The individual bit error can be calculated by: Error [%] + baud rate With: baud rate: Desired baud rate BRCLK: UxBR:...
Page 274 USART Operation: UART Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 13−9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock.
Page 275 For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB of UxMCTL is used first.
Page 276 USART Operation: UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 13−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit.
Page 277: Usart Interrupts
13.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set.
Page 278 USART Operation: UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1.
Page 279 Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation. The ultra-fast turn-on of the DCO allows character reception after the start edge detection.
Page 280 USART Operation: UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t (approximately 300 ns) will be ignored by the USART and no interrupt request will be generated as shown in Figure 13−12.
Page 281: Usart Registers: Uart Mode
13.3 USART Registers: UART Mode Table 13−3 lists the registers for all devices implementing a USART module. Table 13−4 applies only to devices with a second USART module, USART1. Table 13−3.USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0...
Page 282 USART Registers: UART Mode UxCTL, USART Control Register PENA rw−0 rw−0 rw−0 PENA Bit 7 Parity enable Parity disabled. Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Bit 6 Parity select.
Page 283 UxTCTL, USART Transmit Control Register Unused CKPL SSELx rw−0 rw−0 rw−0 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select UCLKI = UCLK UCLKI = inverted UCLK SSELx Bits Source select. These bits select the BRCLK source clock. UCLKI ACLK SMCLK SMCLK...
Page 284 USART Registers: UART Mode UxRCTL, USART Receive Control Register rw−0 rw−0 rw−0 Bit 7 Framing error flag No error Character received with low stop bit Bit 6 Parity error flag. When PENA = 0, PE is read as 0. No error Character received with parity error Bit 5 Overrun error flag.
Page 285 UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 2 15 2 14 2 13 The valid baud-rate control range is 3 ≤ UxBR < 0FFFFh, where UxBR = UxBRx {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR <3.
Page 286 USART Registers: UART Mode UxRXBUF, USART Receive Buffer Register UxRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
Page 287 ME1, Module Enable Register 1 UTXE0 † URXE0 † rw−0 rw−0 † UTXE0 Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0. Module not enabled Module enabled † URXE0 Bit 6 USART0 receive enable. This bit enables the receiver for USART0. Module not enabled Module enabled Bits...
Page 288 USART Registers: UART Mode IE1, Interrupt Enable Register 1 UTXIE0 † URXIE0 † rw−0 rw−0 † UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled † URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. Interrupt not enabled Interrupt enabled Bits...
Page 289 IFG1, Interrupt Flag Register 1 UTXIFG0 † URXIFG0 † rw−1 rw−0 † UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending † URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
Page 290 USART Registers: UART Mode ‡ UTXIFG0 Bit 1 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending ‡ URXIFG0 Bit 0 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. No interrupt pending Interrupt pending ‡...
Page 291 USART Peripheral Interface, UART Mode 13-31...
Page 292: Usart Peripheral Interface, Spi Mode
USART Peripheral Interface, SPI Mode universal synchronous/asynchronous peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430x12xx, MSP430x13xx, and MSP430x15x devices. In addition to USART0, the MSP430x14x and MSP430x16x devices implement a second identical USART module, USART1.
Page 293: Usart Introduction: Spi Mode
USART Introduction: SPI Mode 14.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared. SPI mode features include: 7- or 8-bit data length 3-pin and 4-pin SPI operation...
Page 294 Figure 14−1. USART Block Diagram: SPI Mode SWRST USPIEx* URXEIE URXWIE Receive Control Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 CHAR Baud−Rate Generator UCLKI ACLK Prescaler/Divider UxBRx SMCLK SMCLK Modulator UxMCTL CHAR Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF UTXIFGx*...
Page 295: Usart Initialization And Reset
USART Operation: SPI Mode 14.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: SIMO SOMI...
Page 296 14.2.2 Master Mode Figure 14−2. USART Master and External Slave MASTER Receive Buffer UxRXBUF Transmit Buffer UxTXBUF Receive Shift Register Transmit Shift Register MSP430 USART Figure 14−2 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates data transfer when data is moved to the transmit data buffer UxTXBUF.
Page 297: Slave Mode
USART Operation: SPI Mode 14.2.3 Slave Mode Figure 14−3. USART Slave and External Master MASTER SIMO SPI Receive Buffer Px.x SOMI Data Shift Register DSR SCLK COMMON SPI Figure 14−3 shows the USART as a slave in both 3-pin and 4-pin configurations.
Page 298: Spi Enable
14.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated.
Page 299 USART Operation: SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 14−6 and Figure 14−7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register. Figure 14−6. SPI Master Receive-Enable State Diagram USPIEx = 0 USPIEx = 1 Receive...
Page 300: Serial Clock Control
14.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 14−8. When MM = 0, the USART clock is provided on the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are don’t care.
Page 301 USART Operation: SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART. Timing for each case is shown in Figure 14−9. Figure 14−9. USART SPI Timing Cycle# CKPH CKPL UCLK...
Page 302: Spi Interrupts
14.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set.
Page 303 USART Operation: SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 14−11 and Figure 14−12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1.
Page 304: Usart Registers: Spi Mode
14.3 USART Registers: SPI Mode The USART registers, shown in Table 14−1 and Table 14−2, are byte structured and should be accessed using byte instructions. Table 14−1.USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1...
Page 305 USART Registers: SPI Mode UxCTL, USART Control Register I2C † Unused Unused rw−0 rw−0 rw−0 Unused Bits Unused 7−6 † Bit 5 I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. SPI mode C mode CHAR Bit 4 Character length...
Page 306 UxTCTL, USART Transmit Control Register CKPH CKPL SSELx rw−0 rw−0 rw−0 CKPH Bit 7 Clock phase select. Controls the phase of UCLK. Normal UCLK clocking scheme UCLK is delayed by one half cycle CKPL Bit 6 Clock polarity select The inactive level is low; data is output with the rising edge of UCLK; input data is latched with the falling edge of UCLK.
Page 307 USART Registers: SPI Mode UxRCTL, USART Receive Control Register Unused rw−0 rw−0 rw−0 Bit 7 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. No conflict detected A negative edge occurred on STE, indicating bus conflict Undefined Bit 6...
Page 308 UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 2 15 2 14 2 13 UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. UxMCTL, USART Modulation Control Register UxMCTLx Bits...
Page 309 USART Registers: SPI Mode UxRXBUF, USART Receive Buffer Register UxRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
Page 310 ME1, Module Enable Register 1 USPIE0 † rw−0 Bit 7 This bit may be used by other modules. See device-specific datasheet. † USPIE0 Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0. Module not enabled Module enabled Bits These bits may be used by other modules.
Page 311 USART Registers: SPI Mode IE1, Interrupt Enable Register 1 UTXIE0 † URXIE0 † rw−0 rw−0 † UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled † URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. Interrupt not enabled Interrupt enabled Bits...
Page 312 ‡ UTXIE0 Bit 1 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled ‡ URXIE0 Bit 0 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt for USART0. Interrupt not enabled Interrupt enabled ‡...
Page 313 USART Registers: SPI Mode IFG1, Interrupt Flag Register 1 UTXIFG0 † URXIFG0 † rw−1 rw−0 † UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending † URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
Page 314 USART Peripheral Interface, SPI Mode 14-23...
Page 315: Usart Peripheral Interface, I
USART Peripheral Interface, I universal synchronous/asynchronous peripheral interface supports I C communication in USART0. This chapter describes the I C mode. The I C mode is implemented on the MSP430x15x and MSP430x16x devices. Topic 15.1 I C Module Introduction ........15.2 I C Module Operation .
Page 316 C Module Introduction 15.1 I C Module Introduction The inter-IC control (I and I C-compatible devices connected by way of the two-wire I External components attached to the I serial data to/from the USART through the 2-wire I The I C module has the following features: Compliance to the Philips Semiconductor I Byte/word format transfer...
Page 317 Figure 15−1. USART Block Diagram: I I2CSSELx I2CBUSY No clock ACLK I2CIN SMCLK SMCLK I2CRXOVR Receive Shift Register I2CSBD I2CWORD I2CDRW I2COA I2CSA C Mode I2CEN I2C Clock Generator I2CPSC I2CSCLL I2CCLK I2CSCLH I2CTRX LISTEN I2CSTP I2CSTT I2CSTB Transmit Shift Register I2CTXUDF I2CNDATx USART Peripheral Interface, I...
Page 318 C Module Operation 15.2 I C Module Operation The I C module supports any slave or master I Figure 15−2 shows an example of an I by a unique address and can operate as either a transmitter or a receiver. A device connected to the I when performing data transfers.
Page 319 15.2.1 I C Module Initialization The I C module is part of the USART peripheral. Individual bit definitions when using USART0 in I default value for the U0CTL register is the UART mode. To select I the SYNC and I2C bits must be set. After module initialization, the I is ready for transmit or receive operation.
Page 320 C Module Operation 15.2.2 I C Serial Data One clock pulse is generated by the master device for each data bit transferred. The I significant bit first as shown in Figure 15−3. The first byte after a START condition consists of a 7-bit slave address and the R/W bit.
Page 321 15.2.3 I C Addressing Modes The I C module supports 7-bit and 10-bit addressing modes. 7-Bit Addressing In the 7-bit addressing format, shown in Figure 15−5, the first byte is the 7-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte.
Page 322: Master Mode
C Module Operation 15.2.4 I C Module Operating Modes The I C module operates in master transmitter, master receiver, slave transmitter, or slave receiver mode. Master Mode In master mode, transmit and receive operation is controlled with the I2CRM, I2CSTT, and I2CSTP bits as described in Table 15−1. The master transmitter and master receiver modes are shown in Figure 15−8 and Figure 15−9.
Page 323 Figure 15−8. Master Transmitter Mode IDLE I2CSTT=1 4 x I2CPSC Generate START I2CBUSY Is Set 8 x I2CPSC I2CBB Is Set I2CSTT Is Cleared 8 x SCL XA=0 8 x SCL 8 x SCL Send Slave Address Bits 6−0 with R/W=0 No Ack I2CRM=0 Repeat Mode?
Page 324 C Module Operation Figure 15−9. Master Receiver Mode IDLE I2CSTT=1 4 x I2CPSC Generate START 8 x I2CPSC I2CBB Is Set I2CSTT Is Cleared XA = 1 8 x SCL Send Slave Address Bits 9−8 Extended With R/W = 0 XA = 0 8 x SCL Send Slave Address...
Page 325 Arbitration If two or more master transmitters simultaneously start a transmission on the bus, an arbitration procedure is invoked. Figure 15−10 illustrates the arbitration procedure between two devices. The arbitration procedure uses the data presented on SDA by the competing transmitters. The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low.
Page 326 C Module Operation Automatic Data Byte Counting Automatic data byte counting is supported in master mode with the I2CNDAT register. When I2CRM = 0, the number of bytes to be received or transmitted is written to I2CNDAT. A STOP condition is automatically generated after I2CNDAT number of bytes have been transferred.
Page 327 Figure 15−11.Slave Transmitter IDLE START Detected? STTIFG Is Set I2CBUSY Is Set 4 x I2CPSC I2CBB Is Set XA = 1 XA = 0 8 x SCL 8 x SCL Receive Slave Receive Slave Address Bits 6−0 Address Bits 9−8 with R/W = 1 with R/W = 0 Match...
Page 328 C Module Operation Figure 15−12. Slave Receiver IDLE START Detected? STTIFG Is Set I2CBUSY Is Set 4 x I2CPSC I2CBB Is Set XA = 1 XA = 0 8 x SCL 8 x SCL Receive Slave Receive Slave Address Bits 9−8 Address Bits 6−0 with R/W = 0 with R/W = 0...
Page 329 15.2.5 The I C Data Register I2CDR The I2CDR register can be accessed as an 8-bit or 16-bit register selected by the I2CWORD bit. The I2CDR register functions as described in Table 15−2. When I2CWORD = 1, any attempt to modify the register with a byte instruction will fail and the register will not be modified.
Page 330 C Module Operation 15.2.6 I C Clock Generation and Synchronization The I C module is operated with the clock source selected by the I2CSSELx bits. The prescaler, I2CPSC, and the I2CSCLH and I2CSCLL registers determine the frequency and duty cycle of the SCL clock signal for master mode as shown in Figure 15−13.
Page 331 15.2.7 Using the I C Module with Low Power Modes The I C module can be used with MSP430 low-power modes. When the internal clock source for the I normally regardless of the MSP430 operating mode. When the internal clock source for the I provided.
Page 332 C Module Operation 15.2.8 I C Interrupts The I C module has one interrupt vector for eight interrupt flags listed in Table 15−3. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt request.
Page 333 I2CIV, Interrupt Vector Generator The I C interrupt flags are prioritized and combined to source a single interrupt vector. The interrupt vector register I2CIV is used to determine which flag requested an interrupt. The highest priority enabled interrupt generates a number in the I2CIV register that can be evaluated or added to the program counter to automatically enter the appropriate software routine.
Page 334: I 2 C Module Registers
C Module Registers 15.3 I C Module Registers The I C module registers are listed in Table 15−4. Table 15−4.I C Registers Register C interrupt enable C interrupt flag C data count USART control C transfer control C data control C prescaler C SCL high C SCL low...
Page 335 U0CTL, USART0 Control Register-I RXDMAEN TXDMAEN rw−0 rw−0 rw−0 RXDMAEN Bit 7 Receive DMA enable. This bit enables the DMA controller to be used to transfer data from the I RXDMAEN = 1, RXRDYIE is ignored. Disabled Enabled TXDMAEN Bit 6 Transmit DMA enable.
Page 336 C Module Registers I2CTCTL, I C Transmit Control Register I2CWORD I2CRM I2CSSELx rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CWORD Bit 7 C word mode. Selects byte or word mode for the I Byte mode Word mode I2CRM Bit 6 C repeat mode I2CNDAT defines the number of bytes transmitted.
Page 337 I2CDCTL, I C Data Control Register Unused Unused I2CBUSY r−0 Unused Bits Unused. Always read as 0. 7−6 I2CBUSY Bit 5 C busy C module is idle C module is not idle Bit 4 C SCL low. This bit indicates if a slave is holding the SCL line low while the SCLLOW MSP430 is the master and is unused in slave mode.
Page 338 C Module Registers I2CDRW, I2CDRB, I C Data Register rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 I2CDRW/ Bits C Data. When I2CWORD = 1, the register name is I2CDRW. When I2CDRB 15−8 I2CWORD = 0, the name is I2CDRB. When I2CWORD = 1, any attempt to modify the register with a byte instruction will fail and the register will not be updated.
Page 339 I2CPSC, I C Clock Prescaler Register rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CPSCx Bits C clock prescaler. The I 7−0 to produce the internal I I2CPSCx values > 4 are not recommended. The I2CSCLL and I2CSCLH registers should be used to set the SCL frequency. 000h Divide by 1 001h Divide by 2 0FFh Divide by 256...
Page 340 C Module Registers I2CSCLH, I C Shift Clock High Register rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CSCLHx Bits C shift clock high. These bits define the high period of SCL when the I 7−0 controller is in master mode. The SCL high period is (I2CSCLH+2) x (I2CPSC + 1).
Page 341 I2COA, I C Own Address Register, 7-Bit Addressing Mode rw−0 rw−0 Modifiable only when I2CEN = 0 I2COAx Bits C own address. The I2COA register contains the local address of the 15-0 MSP430 I C controller. The I2COA register is right-justified. Bit 6 is the MSB. Bits 15-7 are always 0.
Page 342 C Module Registers I2CSA, I C Slave Address Register, 7-Bit Addressing Mode rw−0 rw−0 I2CSAx Bits C slave address. The I2CSA register contains the slave address of the 15-0 external device to be addressed by the MSP430. It is only used in master mode.
Page 343 I2CIE, I C Interrupt Enable Register STTIE GCIE TXRDYIE rw−0 rw−0 rw−0 STTIE Bit 7 START detect interrupt enable Interrupt disabled Interrupt enabled GCIE Bit 6 General call interrupt enable Interrupt disabled Interrupt enabled TXRDYIE Bit 5 Transmit ready interrupt enable. When TXDMAEN = 1, TXRDYIE is ignored and TXRDYIFG will not generate an interrupt.
Page 344 C Module Registers I2CIFG, I C Interrupt Flag Register STTIFG GCIFG TXRDYIFG rw−0 rw−0 rw−0 STTIFG Bit 7 START detect interrupt flag No interrupt pending Interrupt pending GCIFG Bit 6 General call interrupt flag No interrupt pending Interrupt pending TXRDYIFG Bit 5 Transmit ready interrupt flag No interrupt pending...
Page 345 I2CIV, I C Interrupt Vector Register I2CIVx Bits C interrupt vector value 15-0 I2CIV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h I2CIVx r−0 r−0 r−0 Interrupt Flag Interrupt Source No interrupt pending − Arbitration lost ALIFG No acknowledgement NACKIFG Own address OAIFG...
Page 346 15-32 USART Peripheral Interface, I C Mode...
Page 347: Comparator_A Introduction
Comparator_A is an analog voltage comparator. This chapter describes Comparator_A. Comparator_A MSP430x12x, MSP430x13x, MSP430x14x, MSP430x15x and MSP430x16x devices. Topic 16.1 Comparator_A Introduction ........16.2 Comparator_A Operation .
Page 348: Comparator_A Introduction
Comparator_A Introduction 16.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A include: Inverting and non-inverting terminal input multiplexer Software selectable RC-filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator...
Page 349 Figure 16−1. Comparator_A Block Diagram V CC CAEX P2CA0 − − P2CA1 CAREFx CARSEL V CAREF CAON Tau ~ 2.0ms 0.5x V CC 0.25x V CC Comparator_A Introduction CCI1B CAOUT Set_CAIFG Comparator_A 16-3...
Page 350: Input Analog Switches
Comparator_A Operation 16.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 16.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the –...
Page 351: Voltage Reference Generator
16.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small.
Page 352: Comparator_A, Port Disable Register Capd
Comparator_A Operation 16.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from V parasitic current occurs if the input voltage is near the transition level of the gate.
Page 353: Comparator_A Used To Measure Resistive Elements
16.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 16−5.
Page 354 Comparator_A Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 16−6. Figure 16−6. Timing for Temperature Measurement Systems 0.25 × V Phase I: Charge The V voltage conversion, but are not critical since they cancel in the ratio: –R...
Page 355: Comparator_A Registers
16.3 Comparator_A Registers The Comparator_A registers are listed in Table 16−1: Table 16−1.Comparator_A Registers Register Comparator_A control register 1 Comparator_A control register 2 Comparator_A port disable Short Form Register Type Address CACTL1 Read/write 059h CACTL2 Read/write 05Ah CAPD Read/write 05Bh Comparator_A Registers Initial State Reset with POR...
Page 356 Comparator_A Registers CACTL1, Comparator_A Control Register 1 CAEX CARSEL CAREFx rw−(0) rw−(0) rw−(0) CAEX Bit 7 Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output. CARSEL Bit 6 Comparator_A reference select. This bit selects which terminal the V is applied to.
Page 357 CACTL2, Comparator_A, Control Register Unused rw−(0) rw−(0) rw−(0) Bits Unused. Unused Bit 3 Pin to CA1. This bit selects the CA1 pin function. P2CA1 The pin is not connected to CA1 The pin is connected to CA1 Bit 2 Pin to CA0. This bit selects the CA0 pin function. P2CA0 The pin is not connected to CA0 The pin is connected to CA0...
Page 358 16-12 Comparator_A...
Page 359: Adc12 Introduction
The ADC12 module is a high-performance 12-bit analog-to-digital converter. This chapter describes the ADC12. The ADC12 is implemented in the MSP430x13x, MSP430x14x, MSP430x15x, and MSP430x16x devices. Topic 17.1 ADC12 Introduction ......... . 17.2 ADC12 Operation .
Page 360: Adc12 Introduction
ADC12 Introduction 17.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. ADC12 features include: Greater than 200 ksps maximum conversion rate Monotonic 12-bit converter with no missing codes...
Page 361 Figure 17−1. ADC12 Block Diagram Ve REF+ V REF+ V REF− / Ve REF− INCHx AV SS 0000 SREF2 0001 0001 0010 0011 V R− Sample 0100 0101 12−bit SAR Hold 0110 0111 Convert 1000 1001 1010 1011 1100 1101 1110 1111 SAMPCON...
Page 362: Bit Adc Core
ADC12 Operation 17.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 17.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores programmable/selectable voltage levels (V lower limits of the conversion.
Page 363: Adc12 Inputs And Multiplexer
17.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 17−2. The input multiplexer is also a T-switch to minimize the coupling between channels.
Page 364: Voltage Reference Generator
ADC12 Operation 17.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used internally and externally on pin V Setting REFON=1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V, the reference is 1.5 V when REF2_5V = 0.
Page 365: Sample And Conversion Timing
17.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: The ADC12SC bit The Timer_A Output Unit 1 The Timer_B Output Unit 0 The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit.
Page 366 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period The sampling timer keeps SAMPCON high after synchronization with sample.
Page 367 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t input resistance R by the source. The capacitor C of the source voltage V Figure 17−5.
Page 368: Adc12 Conversion Modes
ADC12 Operation 17.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a sequential conversion mode is used.
Page 369 Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 17−6 shows the flow of the Single-Channel, Single-Conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit.
Page 370 ADC12 Operation Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 17−7 shows the sequence-of-channels mode.
Page 371 Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 17−8 shows repeat-single-channel mode Figure 17−8.
Page 372 ADC12 Operation Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re-starts the sequence.
Page 373 Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion.
Page 374: Using The Integrated Temperature Sensor
ADC12 Operation 17.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc.
Page 375: Adc12 Grounding And Noise Considerations
17.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry.
Page 376: Adc12 Interrupts
ADC12 Operation 17.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: ADC12IFG0-ADC12IFG15 ADC12OV, ADC12MEMx overflow ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set.
Page 377 ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 378: Adc12 Registers
ADC12 Registers 17.3 ADC12 Registers The ADC12 registers are listed in Table 17−2: Table 17−2.ADC12 Registers Register ADC12 control register 0 ADC12 control register 1 ADC12 interrupt flag register ADC12 interrupt enable register ADC12 interrupt vector word ADC12 memory 0 ADC12 memory 1 ADC12 memory 2 ADC12 memory 3...
Page 379 ADC12CTL0, ADC12 Control Register 0 SHT1x rw−(0) rw−(0) rw−(0) REF2_5V REFON rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 SHT1x Bits Sample-and-hold time. These bits define the number of ADC12CLK cycles in 15-12 the sampling period for registers ADC12MEM8 to ADC12MEM15. SHT0x Bits Sample-and-hold time.
Page 380 ADC12 Registers Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes. The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed.
Page 381 ADC12CTL1, ADC12 Control Register 1 CSTARTADDx rw−(0) rw−(0) rw−(0) ADC12DIVx rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 CSTART Bits Conversion ADDx 15-12 conversion-memory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15.
Page 382 ADC12 Registers ADC12 Bits ADC12 clock source select SSELx ADC12OSC ACLK MCLK SMCLK CONSEQx Bits Conversion sequence mode select Single-channel, single-conversion Sequence-of-channels Repeat-single-channel Repeat-sequence-of-channels ADC12 Bit 0 ADC12 busy. This bit indicates an active sample or conversion operation. BUSY No operation is active. A sequence, sample, or conversion is active.
Page 383 ADC12MCTLx, ADC12 Conversion Memory Control Registers SREFx rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 Bit 7 End of sequence. Indicates the last conversion in a sequence. Not end of sequence End of sequence SREFx Bits Select reference 000 V = AV 001 V 010 V...
Page 384 ADC12 Registers ADC12IE, ADC12 Interrupt Enable Register ADC12IE15 ADC12IE14 ADC12IE13 rw−(0) rw−(0) rw−(0) ADC12IE7 ADC12IE6 ADC12IE5 rw−(0) rw−(0) rw−(0) ADC12IEx Bits Interrupt enable. These bits enable or disable the interrupt request for the 15-0 ADC12IFGx bits. Interrupt disabled Interrupt enabled ADC12IFG, ADC12 Interrupt Flag Register ADC12 ADC12...
Page 385 ADC12IV, ADC12 Interrupt Vector Register r−(0) ADC12IVx Bits ADC12 interrupt vector value 15-0 ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h ADC12IVx r−(0) r−(0) r−(0) Interrupt Source Interrupt Flag No interrupt pending −...
Page 386 17-28 ADC12...
Page 387: Adc10
The ADC10 module is a high-performance 10-bit analog-to-digital converter. This chapter describes the ADC10. The ADC10 is implemented in the MSP430x11x2, MSP430x12x2 devices. Topic 18.1 ADC10 Introduction ......... . 18.2 ADC10 Operation .
Page 388: Adc10 Introduction
ADC10 Introduction 18.1 ADC10 Introduction The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC). The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention.
Page 389 Figure 18−1. ADC10 Block Diagram REFOUT Ve REF+ V REF+ V REF− / Ve REF− INCHx Auto CONSEQx V SS 0000 SREF2 0001 0001 0010 0011 V R− Sample 0100 0101 10−bit SAR Hold 0110 0111 Convert 1000 1001 1010 1011 1100 1101...
Page 390: Adc10 Operation
ADC10 Operation 18.2 ADC10 Operation The ADC10 module is configured with user software. The setup and operation of the ADC10 is discussed in the following sections. 18.2.1 10-Bit ADC Core The ADC core converts an analog input to its 10-bit digital representation and stores the result in the ADC10MEM register.
Page 391: Adc10 Inputs And Multiplexer
18.2.2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 18−2. The input multiplexer is also a T-switch to minimize the coupling between channels.
Page 392: Voltage Reference Generator
ADC10 Operation 18.2.3 Voltage Reference Generator The ADC10 module contains a built-in voltage reference with two selectable voltage levels. Setting REFON = 1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V. When REF2_5V = 0, the reference is 1.5 V.
Page 393: Sample And Conversion Timing
18.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: The ADC10SC bit The Timer_A Output Unit 1 The Timer_A Output Unit 0 The Timer_A Output Unit 2 The polarity of the SHI signal source can be inverted with the ISSH bit.
Page 394 ADC10 Operation Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t input resistance R by the source. The capacitor C of the source voltage V Figure 18−4.
Page 395: Conversion Modes
18.2.6 Conversion Modes The ADC10 has four operating modes selected by the CONSEQx bits as discussed in Table 18−1. Table 18−1.Conversion Mode Summary CONSEQx Mode Operation Single channel A single channel is converted once. single-conversion Sequence-of- A sequence of channels is converted once. channels Repeat single A single channel is converted repeatedly.
Page 396 ADC10 Operation Single-Channel Single-Conversion Mode A single channel selected by INCHx is sampled and converted once. The ADC result is written to ADC10MEM. Figure 18−5 shows the flow of the single-channel, single-conversion mode. When ADC10SC triggers a conversion, successive conversions can be triggered by the ADC10SC bit. When any other trigger source is used, ENC must be toggled between each conversion.
Page 397 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence stops after conversion of channel A0. Figure 18−6 shows the sequence-of-channels mode.
Page 398 ADC10 Operation Repeat-Single-Channel Mode A single channel selected by INCHx is sampled and converted continuously. Each ADC result is written to ADC10MEM. Figure 18−7 shows the repeat-single-channel mode. Figure 18−7. Repeat-Single-Channel Mode CONSEQx = 10 ADC10ON = 1 SHS = 0 ENC = 1 or ADC10SC = MSC = 1...
Page 399 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence ends after conversion of channel A0, and the next trigger signal re-starts the sequence. Figure 18−8 shows the repeat-sequence-of-channels mode.
Page 400 ADC10 Operation Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1 and CONSEQx > 0 the first rising edge of the SHI signal triggers the first conversion.
Page 401: Adc10 Data Transfer Controller
18.2.7 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller (DTC) to automatically transfer conversion results from ADC10MEM to other on-chip memory locations. The DTC is enabled by setting the ADC10DTC1 register to a nonzero value. When the DTC is enabled, each time the ADC10 completes a conversion and loads the result to ADC10MEM, a data transfer is triggered.
Page 402 ADC10 Operation One-Block Transfer Mode The one-block mode is selected if the ADC10TB is reset. The value n in ADC10DTC1 defines the total number of transfers for a block. The block start address is defined anywhere in the MSP430 address range using the 16-bit register ADC10SA.
Page 403 Figure 18−10. State Diagram for Data Transfer Control in One-Block Transfer Mode DTC reset n ≠ 0 n = 0 DTC init Write to ADC10SA x = n AD = SA Write to ADC10SA n = 0 DTC idle Write to ADC10MEM completed Write to ADC10SA Wait...
Page 404 ADC10 Operation Two-Block Transfer Mode The two-block mode is selected if the ADC10TB bit is set. The value n in ADC10DTC1 defines the number of transfers for one block. The address range of the first block is defined anywhere in the MSP430 address range with the 16-bit register ADC10SA.
Page 405 Figure 18−12. State Diagram for Data Transfer Control in Two-Block Transfer Mode DTC reset ADC10B1 = 0 ADC10TB = 1 n = 0 DTC init If ADC10B1 = 0 then AD = SA Write to ADC10SA n = 0 DTC idle Write to ADC10SA CPU ready Write to ADC10SA...
Page 406 ADC10 Operation Continuous Transfer A continuous transfer is selected if ADC10CT bit is set. The DTC will not stop after block one in (one-block mode) or block two (two-block mode) has been transferred. The internal address pointer and transfer counter are set equal to ADC10SA and n respectively.
Page 407: Using The Integrated Temperature Sensor
18.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc. The typical temperature sensor transfer function is shown in Figure 18−13.
Page 408: Adc10 Grounding And Noise Considerations
ADC10 Operation 18.2.9 ADC10 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry.
Page 409: Adc10 Interrupts
18.2.10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 18−17. When the DTC is not used (ADC10DTC1 = 0) ADC10IFG is set when conversion results are loaded into ADC10MEM. When DTC is used (ADC10DTC1 > 0) ADC10IFG is set when a block transfer completes and the internal transfer counter ’n’...
Page 410: Adc10 Registers
ADC10 Registers 18.3 ADC10 Registers The ADC10 registers are listed in Table 18−3. Table 18−3.ADC10 Registers Register ADC10 Input enable register ADC10 control register 0 ADC10 control register 1 ADC10 memory ADC10 data transfer control register 0 ADC10DTC0 ADC10 data transfer control register 1 ADC10DTC1 ADC10 data transfer start address 18-24 ADC10...
Page 411 ADC10CTL0, ADC10 Control Register 0 SREFx rw−(0) rw−(0) rw−(0) REF2_5V REFON rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 SREFx Bits Select reference 15-13 000 V 001 V 010 V = Ve 011 V = Ve 100 V 101 V 110 V = Ve 111 V...
Page 412 ADC10 Registers Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes. The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion. The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed REF2_5V...
Page 413 ADC10CTL1, ADC10 Control Register 1 INCHx rw−(0) rw−(0) rw−(0) ADC10DIVx rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 INCHx Bits Input channel select. These bits select the channel for a single-conversion or 15-12 the highest channel for a sequence of conversions. 0000 0001 0010...
Page 414 ADC10 Registers ADC10DIVx Bits ADC10 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8 ADC10 Bits ADC10 clock source select SSELx ADC10OSC ACLK MCLK SMCLK CONSEQx Bits Conversion sequence mode select Single-channel-single-conversion Sequence-of-channels Repeat-single-channel...
Page 415 ADC10MEM, Conversion-Memory Register, Binary Format Conversion Bits The 10-bit conversion results are right justified, straight-binary format. Bit 9 Results 15-0 is the MSB. Bits 15-10 are always 0. ADC10MEM, Conversion-Memory Register, 2’s Complement Format Conversion Results Conversion Bits The 10-bit conversion results are left-justified, 2’s complement format. Bit 15 Results 15-0 is the MSB.
Page 416 ADC10 Registers ADC10DTC0, Data Transfer Control Register 0 Reserved Reserved Bits Reserved. Always read as 0. ADC10TB Bit 3 ADC10 two-block mode. One-block transfer mode Two-block transfer mode ADC10CT Bit 2 ADC10 continuous transfer. Data transfer stops when one block (one-block mode) or two blocks (two-block mode) have completed.
Page 417 ADC10DTC1, Data Transfer Control Register 1 rw−(0) rw−(0) rw−(0) Bits DTC transfers. These bits define the number of transfers in each block. Transfers DTC is disabled 01h-0FFh Number of transfers per block ADC10SA, Start Address Register for Data Transfer rw−(0) rw−(0) rw−(0) rw−(0)
Page 418 18-32 ADC10...
Page 419: Dac12
The DAC12 module is a 12-bit, voltage output digital-to-analog converter. This chapter describes the DAC12. Two DAC12 modules are implemented in the MSP430x15x and MSP430x16x devices. Topic 19.1 DAC12 Introduction ......... . 19.2 DAC12 Operation .
Page 420: Dac12 Introduction
DAC12 Introduction 19.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
Page 421 Figure 19−1. DAC12 Block Diagram Ve REF+ To ADC12 module V REF+ 2.5V or 1.5V reference from ADC12 DAC12SREFx DAC12LSELx Latch Bypass DAC12GRP DAC12_0DAT Updated Group Load Logic DAC12SREFx DAC12LSELx Latch Bypass DAC12GRP DAC12_1DAT Updated DAC12AMPx DAC12IR AV SS V R− V R+ DAC12_0 DAC12_0Latch...
Page 422: Dac12 Operation
DAC12 Operation 19.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 19.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using the DAC12RES bit.
Page 423: Updating The Dac12 Voltage Output
19.2.2 DAC12 Reference The reference for the DAC12 is configured to use either an external reference voltage or the internal 1.5-V/2.5-V reference from the ADC12 module with the DAC12SREFx bits. When DAC12SREFx = {0,1} the V the reference and when DAC12SREFx = {2,3} the Ve reference.
Page 424: Dac12_Xdat Data Format
DAC12 Operation 19.2.4 DAC12_xDAT Data Format The DAC12 supports both straight binary and 2’s compliment data formats. When using straight binary data format, the full-scale output value is 0FFFh in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 19−2. Figure 19−2.
Page 425: Dac12 Output Amplifier Offset Calibration
19.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative. When the offset is negative, the output amplifier attempts to drive the voltage negative, but cannot do so. The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19−4.
Page 426: Grouping Multiple Dac12 Modules
DAC12 Operation 19.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event. On the MSP430x15x and MSP430x16x devices, DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0.
Page 427: Dac12 Interrupts
DAC12 Operation 19.2.7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller. Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt. The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch.
Page 428: Dac12 Registers
DAC12 Registers 19.3 DAC12 Registers The DAC12 registers are listed in Table 19−2: Table 19−2.DAC12 Registers Register DAC12_0 control DAC12_0 data DAC12_1 control DAC12_1 data 19-10 DAC12 Short Form Register Type Address DAC12_0CTL Read/write 01C0h DAC12_0DAT Read/write 01C8h DAC12_1CTL Read/write 01C2h DAC12_1DAT Read/write...
Page 429 DAC12_xCTL, DAC12 Control Register Reserved DAC12SREFx rw−(0) rw−(0) rw−(0) DAC12AMPx rw−(0) rw−(0) rw−(0) Modifiable only when DAC12ENC = 0 Reserved Bit 15 Reserved DAC12 Bits DAC12 select reference voltage SREFx 14-13 REF+ REF+ REF+ REF+ DAC12 Bit 12 DAC12 resolution select 12-bit resolution 8-bit resolution DAC12...
Page 430 DAC12 Registers DAC12 Bits DAC12 amplifier setting. These bits select settling time vs. current AMPx consumption for the DAC12 input and output amplifiers. DAC12AMPx DAC12DF Bit 4 DAC12 data format Straight binary 2’s compliment DAC12IE Bit 3 DAC12 interrupt enable Disabled Enabled DAC12IFG...
Page 431 DAC12_xDAT, DAC12 Data Register r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) Unused Bits Unused. These bits are always 0 and do not affect the DAC12 core. 15-12 DAC12 Data Bits DAC12 data 11-0 DAC12 Data Format 12-bit binary 12-bit 2’s complement 8-bit binary 8-bit 2’s complement DAC12 Data...
Page 432 19-14 DAC12...