Ssi Interconnect; Introduction - Texas Instruments OMAP5912 Reference Manual

SSI Interconnect

4 SSI Interconnect
4.1

Introduction

42 Peripheral Interconnects
The following configurations are possible for the buffer block in case of a burst
request transaction:
-
GDD or VLYNQ side, send as soon as possible
-
GDD or VLYNQ side, wait for buffer mode
-
USB side, send as soon as possible mode
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USB side, wait for buffer mode
For all USB, GDD, and VLYNQ simple read or write transactions, the request
is sent directly to the OMAP OCP_I interface.
The SSI interconnect manages accesses to OMAP5912 peripherals through
GDD, acting as a bridge between external serial peripherals (using VIA buses)
and the internal parallel bus (OCP). On one side it is connected to SSI, using
two VIA buses, and on the other to GDD, using an OCP bus (see Figure 9).
The SSI module is composed of two blocks, SSR and SST, each using a
different VIA bus.
SSI interconnect is composed of five blocks:
-
Decode
The decode module dispatches incoming transactions either to OCP to
the VIA asynchronous bridge or to the synchronous bridge of OCP to VIA.
-
OCP to the VIA synchronous bridge
OCP to the VIA synchronous bridge connects SST to GDD via the OCP
bus. Because the SST module is synchronous with the OCP bus, resyn-
chronization is not required and a faster synchronous bridge can be used.
-
OCP to the VIA asynchronous bridge
OCP to the VIA asynchronous bridge connects SSR to the OCP bus. Be-
cause the SSR module works on a clock that is asynchronous and faster
than the OCP bus, resynchronization is required.
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DMA and interrupt formatter
DMA and interrupt formatter is responsible for generating DMA and inter-
rupt requests from the SSR and SST status signals.
SPRU758A