System Dma Interrupt Mapping; Dma Idle Modes; Dynamic Idle Mode - Texas Instruments OMAP5912 Reference Manual

System DMA Interrupt Mapping

3.1.13

DMA IDLE Modes

Dynamic Idle Mode

SPRU755B
When a status event occurs and the corresponding interrupt enable bit is
enabled, the following happens:
The status register bit is activated.
-
An interrupt is generated.
-
No new interrupts can be generated until the status register is read and
-
thereby cleared.
Note:
One read in the status register clears all the status bits.
-
No read in the status register keeps all the status bits and DMA interrupt
-
output stays active low.
Therefore, software must always read the associated status register for each
DMA interrupt received; otherwise, interrupts can be missed.
System DMA interrupt mapping depends on the compatibility mode used.
If the OMAP3_1_COMPATIBLE_DISABLE bit is set to 1 in the DMA_CCR
register, then the system DMA has one interrupt line per logical channel.
If this bit is set to zero, then several channels can share the same interrupt line.
See 3.1.16 for more details.
Each logical channel has an associated status register, DMA_CSR, where the
source of the interrupt is shown.
The system DMA can automatically enter an idle mode dynamically as soon
as it is not active, or it can be put into idle/suspend mode on request from MPU
via the clock generator module.
To save power, the system DMA has a built-in dynamic idle mode that is
enabled by setting the CLOCK_AUTOGATING_ON bit in the global control
register, DMA_GCR.
The system DMA clock domain is split into several subdomains in this mode;
each one of them is disabled if not used. This mode does not add any extra
latency in the system DMA.
Direct Memory Access (DMA) Support
System DMA
59