Interrupt Latency; Interrupt Handler Sleep Mode - Texas Instruments OMAP5912 Reference Manual

2.1.4

Interrupt Latency

2.1.5

Interrupt Handler Sleep Mode

SPRU757B
4) Within the interrupt routine, the host reads the SIR_IRQ register in the
interrupt controller to determine which interrupt line caused the interrupt.
Reading the SIR_IRQ has no effect on the ITR register for the
level-sensitive interrupt, because the interrupt is still asserted at this point.
Based on the content of SIR_IRQ, the host executes specific code.
5) Before jumping out of the interrupt routine, the software must:
Ensure that the peripheral that asserted the interrupt deasserts it.
J
Set the NEW_IRQ_AGR bit of the control register. Setting this bit
J
deasserts the IRQ/FIQ line and enables the interrupt controller to
process any pending interrupts.
To minimize interrupt latency, an IRQ (or FIQ) is generated whenever an
incoming interrupt is detected. Owing to internal resynchronization, the
IRQ/FIQ generation requires three interrupt controller functional clock cycles
to be generated.
The interrupt source calculation (priority handling and SIR register updating)
is made in the background. The interrupt handler stalls any access to the SIR
register until the interrupt source calculation is done.
To avoid unnecessary stalling, the interrupt source calculation does not
depend on the number of incoming interrupts active at the same time. It
depends instead on the total number of incoming interrupts. For the MPU
interrupt handler, the interrupt source calculation requires 10 cycles,
regardless of the number of active incoming interrupts. For the DSP side, the
interrupt source calculation requires 6 cycles.
The MPU can shut off the system clock to save power. The system is
awakened by an asynchronous event, which can be an interrupt. For proper
system operation, the interrupt controller must ensure that no interrupt is
generated when the system is going to power-saving (big or deep sleep)
mode.
Before going to idle, the host sends an idle request (IDLE_REQ) to the
interrupt controller. When the interrupt controller is ready to go to sleep, it
sends back an idle acknowledge (IDLE_ACK) to signal that its functional clock
can be safely shut down. IDLE_REQ/IDLE_ACK handshake is used to prevent
IRQ/FIQ from occurring when the system goes into idle mode. Two different
protocols manage the handshake: FORCE_WAKEUP and SMART_IDLE.
The protocol used is defined by the value of the IDLE_MODE field in the
OCP_CFG register (see Table 18).
Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
Interrupts 23