1.21
32-kHz Oscillator Calibration
Figure 18.
Functional Block Diagram of Gauging
TIPB
register
EXT_HICLK_SEL
46-MHz clock
EXT_HITCH_GAUGING
System clock
32-kHz clock
1.22
Bad Devices
SPRU753A
GAUGING_EN
SELECT_HI_FREQ
TIPB
register
Because the exact 32-kHz clock frequency is unknown, it is necessary to
gauge it by comparing the 32-kHz clock with a higher frequency clock (system
clock, APLL clock out, or EXT_HICLK_GAUGING) during any active period.
Note: Software Limitation
The counter is not resynchronized on the TIPB strobe. Therefore, the value
is not readable while the counter is running (when gauging is enabled). The
procedure is first to disable the gauging (GAUGIG_CTRLREG[0] to 0), and
then to read the counter high frequency and the 32-kHz counter value.
When the DEVICE_TYPE[1:0] indicates that the device is bad
(DEVICE_TYPE = 01), the ULPD keeps both internal cold and warm resets
asserted low. In this configuration the CPU cannot boot.
Note:
DEVICE_TYPE corresponds to EFUSE_DEVICE_TYPE.
Ultralow-Power Device
Clear
Counter high
frequency
OVERFLOW_HI_FREQ
Clear
Counter low
frequency
OVERFLOW_LO_FREQ
Power Management
TIPB
49