Dsp Level 2 Interrupt Handler; Dsp Level 2 Interrupt Mapping - Texas Instruments OMAP5912 Reference Manual

Interrupt Overview
Table 1. DSP Level 1 Interrupt Mapping (Continued)
DSP Soft
Interrupt
Priority
24 SINT23
25 SINT24
26 SINT25
27 SINT26
28 SINT27
29 SINT28
30 SINT29
31 SINT30
32 SINT31
1.1.1

DSP Level 2 Interrupt Handler

1.1.2

DSP Level 2 Interrupt Mapping

12 Interrupts
DSP Hard Location Vectors
Interrupt (Hex/Byte)
INT23 B8
INT24 C0
INT25 C8
INT26 D0
INT27 D8
INT28 E0
INT29 E8
INT30 F0
INT31 F8
The system has two DSP level 2 interrupt handlers. One is in the OMAP3.2
gigacell (the DSP level 2.0 interrupt handler), and the other is outside the
OMAP3.2 gigacell (the DSP level 2.1 interrupt handler):
The DSP level 2.0 interrupt handler handles 16 interrupt lines.
-
The DSP level 2.1 interrupt handler handles 64 interrupt lines.
-
For more detail on the architecture and programming model of the level 2
interrupt handler, see Section 2, Interrupt Controller.
The default interrupt priority for the DSP interrupt handler level 1 can be
remapped by MPU software only when DSP is held in reset. All level 2 interrupt
lines have the same priority by default, which DSP software can modify
through the configuration register in the level 2 interrupt controller.
Function
DSP timer 1 interrupt
Bus error interrupt # 25 BERR
Emulator interrupt # 26 DLOG
Emulator interrupt # 27 RTOS
Software interrupt #28
Software interrupt #29
Software interrupt #30
Software interrupt #31
Software interrupt #32
SPRU757B