Table 4.
DSP Peripherals Connected to DSP Shared TIPB Bridge
Table 5.
DSP and MPU Shared Peripherals
2.2
Protocols
SPRU758A
OMAP 5912 Peripheral
2 x MCSI
2 x McBSP
OMAP 5912 Peripheral
MMCSD/IO2
STI (reserved)
32-kHz synchronization timer
4 x GPIO
GPIO
3 x UART
McBSP
2
I
C
SPI
8 x GP timers
NAND flash control
Static switch configuration
The layer 4 interface is connected to several peripherals, which use different
protocols:
-
TI peripheral bus or TIPB bus
-
Versatile interconnection architecture designated also as VIA bus or VIA
protocol
-
Open core protocol designated as OCP
Layer 4 Interconnect
Interface
TIPB Router
TIPB
Shared DSP
Wrapper OCP
Shared DSP
Interface
TIPB Router
MPU
Static OCP
Shared
Dynamic OCP
Private
Dynamic OCP
Shared
Dynamic OCP
Shared
Dynamic OCP
Shared
Static OCP
Shared
Static OCP
Shared
Static OCP
Shared
Static OCP
Shared
Static OCP
Shared
Static OCP
Shared
TIPB
Shared
Peripheral Interconnects
DSP
Shared
Shared
Shared
Shared
Shared
Shared
Shared
Shared
Shared
Shared
Shared
Shared
23