Interrupt Controllers (Mpu Level 2 And Dsp Level 2.1) - Texas Instruments OMAP5912 Reference Manual

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MPU Level 2 Interrupt Mapping (Continued)

Level 2 Interrupt Line

IRQ_103 ... IRQ_127

These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime-

dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)

Reserved (USB HHC2 suspend)

For each interrupt, the user must configure the SENS_nEDGE bit in the

corresponding interrupt level register (ILR) according to whether the interrupt

is edge or level sensitive. See Table 13 for more details.

The MPU level 2 and DSP level 2.1 interrupt controllers have the same

programming model. The only difference between the two is the number of

interrupts each can handle (128 for MPU level 2 and 64 for DSP level 2.1).

Throughout this section, both interrupt controllers are referred to collectively

as the interrupt controller.

The MPU level 2 interrupt controller functional clock source is ARM_CK or

ARM_CK/2, according to the ARM_CKCTL.ARM_INTHCK_SEL bit.

The DSP level 2.1 interrupt controller functional clock source is the

The interrupt controller is able to handle interrupts coming from different

functional blocks, prioritize them, and route them to a host. It generates one

IRQ and one FIQ signal to the host. Both signals are active low-level interrupts,

synchronous with the interrupt controller functional clock.

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)

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