Asynchronous Transparency; Abort Sequence; Pulse Shaping - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Asynchronous Transparency

Serial Interfaces

Before transmitting a byte, the UART IrDA controller examines each byte of

the payload and the CRC field (between BOF and EOF). For each byte equal

to 0xC0 (BOF), 0xC1 (EOF), or 0x7D (control escape), it does the following.

In transmission:

Inserts a control escape (CE) byte preceding the byte.

Complements bit 5 of the byte (that is, exclusive ORs the byte with 0x20).

The byte sent for the CRC computation is the initial byte written in the TX FIFO

(before the XOR with 0x20).

In reception:

For the A, C, I, and CRC fields:

Compares the byte with the CE byte. If not equal, sends it to the CRC

detector and stores it in the RX FIFO.

If equal to CE, discards the CE byte.

Complements bit 5 of the byte following the CE.

Sends the complemented byte to the CRC detector and stores it in the RX

The transmitter may decide to prematurely close a frame. The transmitter

aborts by sending the 0x7DC1 sequence. The abort pattern closes the frame

without a CRC field or an ending flag.

It is possible to abort a transmission frame by programming the ABORT_EN

bit of the auxiliary control register (ACREG [1]).

When this bit is set to 1, 0x7D and 0xC1 are transmitted and the frame is not

terminated with CRC or stop flags.

The receiver treats a frame as an aborted frame when a 0x7D character

followed immediately by a 0xC1 character is received without transparency.

In SIR mode both the 3/16 and the 1.6 ìs pulse duration methods are

supported. ACREG[7] selects the pulse-width method in transmit mode.

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