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Configuration
Reset Architecture / Configuration
Table 6.
Input/Output for Clock and Reset (Continued)
Pin Name
Dir.
USB.CLK0
OUT
SYS_CLK_
OUT
OUT
CAM.EXCLK
OUT
ULPD_
OUT
DPLL48M
LOW_PWR
OUT
LOW_PWR
OUT
2
Configuration
26
Initialization
Ball
Descrip-
Default Mode in
tion
RESET_MODE 0
W4
Derived
from APLL
clock
B15
System
clock
output
H19
Derived
from
CK_REF
J18
Output from
APLL
T20
Low-voltage
mode
W4
Low-voltage
mode
The configuration module allows software to control the various static modes
supported by the device. This module is the primary point of control for the
following areas of the device:
Functional I/O multiplexing
-
Debug and observation I/O multiplexing
-
I/O gating and inhibiting for power-down modes
-
Pullup and pulldown enable and selection
-
Interface voltage selection
-
Static module configuration
-
Control of clock multiplexing
-
Multiplexing mode status
-
Control of USB integrated transceivers
-
LDO bypassing control
-
Reset control
-
Default Mode in
RESET_MODE 1
No
No
No
Yes
No
No
No
No
No
Yes
Notes
96-MHz APLL
clock divided by 16
Same frequency
as DPLL1 input
(CK_REF)
Camera clock
output
In test/
observability mode
only
High in deep sleep
or can be set high
by software
(POWER_CTRL_
REG[1] if
POWER_CTRL_
REG[0]=1)
Low in deep sleep
mode
SPRU752B
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