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TMS320C55x DSP CPU Overview
Figure 2.
DSP Core and Internal Bus Designations
Private
TIPB
bridge
Shared
T
I
P
B
bridge
M
P
U
I
2
TMS320C55x DSP CPU Overview
18
DSP Subsystem
Trace FIFO
DSP CPU core
plus hardware accelerator
(DCT/IDCT motion estimation
half-pixel interpolation
DMA controller
6 channels, 5 ports
Feedback / test logic
Features for the high-performance, low-power C55x DSP CPU include:
-
Advanced multiple-bus architecture with one internal program memory
bus and five internal data buses (three dedicated to reads and two
dedicated to writes)
C,D,E,F
DMA
EMIF
I-Cache
M
I
F
P,B,C,D,E,F
SARAM
DMA
96K bytes
P,B,C,D,E,F
DARAM
64K bytes
DMA
Instruction
cache
P
3x8K bytes
P,B,C,D
PDROM
32K bytes
SPRU750A
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