Interrupt Processing Sequence; Edge-Triggered Interrupts; Level-Sensitive Interrupts - Texas Instruments OMAP5912 Reference Manual

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
2.1.1

Interrupt Processing Sequence

2.1.2

Edge-Triggered Interrupts

2.1.3

Level-Sensitive Interrupts

22 Interrupts
Although only the IRQ is discussed here, the sequence is the same for FIQ.
The sequence depends, however, on the interrupt sensitivity (level or edge).
1) The interrupt controller module receives incoming interrupts and registers
them in the ITR register.
2) The interrupt controller asserts the IRQ signal and begins priority
calculation. When the highest priority interrupt is known, the source IRQ
register (SIR_IRQ) is updated with the current interrupt number.
The only way to deassert the IRQ that has been sent to the host is to set the
NEW_IRQ_AGR bit in the control register.
3) The host, when it recognizes the interrupt, jumps to the interrupt routine.
4) Within the interrupt routine, the host reads the SIR_IRQ register to
determine which interrupt line caused the interrupt. Reading the SIR_IRQ
resets the interrupt bit in the ITR register. The IRQ/FIQ line, however, stays
asserted. Based on the content of SIR_IRQ, the host executes specific
code.
5) Before jumping out of the interrupt routine, the host must set the
NEW_IRQ_AGR bit of the control register. Setting this bit deasserts the
IRQ line and enables the interrupt controller to process any other pending
interrupts.
1) The interrupt controller receives incoming interrupts. Level-sensitive
interrupts are not registered. The interrupt controller assumes that a
peripheral asserting a level-sensitive interrupt does not deassert it until the
software directs it to do so.
2) The interrupt controller asserts the IRQ signal and begins priority
calculation. When the highest priority interrupt is known, the SIR_IRQ
register is updated to the current interrupt number.
The only way to deassert the IRQ that has been sent to the host is to set the
NEW_IRQ_AGR bit in the control register.
3) The host, when it recognizes the interrupt, jumps to the interrupt routine.
SPRU757B